Publications

A. Journal

1. S.O. Jung, K.W. Kim, S.M. Kang "Low Voltage Swing Clock Domino Logic Incorporating Dual Supply and Threshold Voltages", submitted to IEEE tran on VLSI.
2. S.O. Jung, K.W. Kim, S.M. Kang "Timing Constraints for Domino Logic Gates with Timing Dependent Keepers", accepted to IEEE tran on CAD.
3. S.O. Jung, K.W. Kim, and S.M. Kang "Noise Constrained Transistor Sizing and Power Optimization for Dual Vt Domino Logic", accepted to IEEE tran on VLSI.
4. S.O. Jung, S.M. Kang "High Performance Dynamic Logic Incorporating Gate Voltage Controlled Keeper Structure for Wide Fan-In Gate", IEE Electronics Letters, vol. 38, no. 16, pp.852-853, 2002.
5. S.O. Jung, S.M. Kang "Modular Charge Recycling Pass transistor Logic (MCRPL)", IEE Electronics Letters, vol. 36, no.5 pp.404-405, 2000
6. K.W. Kim, S.O. Jung, Taewhan Kim, and S.M. Kang "Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits", IEE Electronics Letters, vol. 37, no.13, pp.813-814, 2001.
7. C. Kim, S.O. Jung, K.H. Baek, S.M. Kang "High Speed CMOS Circuits with Parallel Dynamic Logic and Speed-enhanced Skewed Static Logic", accepted to IEEE Tran on Circuits and Systems II.
8. K.W. Kim, S.O. Jung, U. Narayanan, C.L. Liu, and S.M. Kang, "Noise-Aware Interconnect Power Optimization in Domino Logic Synthesis," accepted to Tran on VLSI.
9. K.W. Kim, S.O. Jung, T.W. Kim, and S.M. Kang, "Minimum Delay Optimization for Domino Logic Circuits - A Coupling-Aware Approach," accepted to TODAES
10. K.W. Kim, S.O. Jung, T.W. Kim, P. Saxena, C.L. Liu and S.M. Kang, "Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique", submitted to Tran on VLSI.
11. C.W. Kim, S.M. Yoo, S.O. Jung, K.H. Baek and S.M. Kang, " New Current S ense Amplifier for High Density DRAMs with Copper Interconnects", submitted to I EE Proceedings of Circuits, Devices and Systems.

B. Conference

1. S.O. Jung, K.W. Kim, and S.M. Kang "Low-Swing Clock Domino Logic Incorporating Dual Threshold and Dual Supply Voltages" ACM / IEEE Design Automation Conference, pp.467-472, 2002.
2. S.O. Jung, K.W. Kim, and S.M. Kang "Optimal Timing for Skew-Tolerant High-Speed Domino Logic" IEEE Computer Society Annual Symposium on VLSI, pp.41-46, 2002.
3. S.O. Jung, K.W. Kim, and S.M. Kang "Dual Threshold Voltage Domino Logic Synthesis for High Performance with Delay and Power Constraint" Design, Automation and Test in Europe, pp.260-265, 2002.
4. S.O. Jung, S. M. Yoo, K.W. Kim, and S.M. Kang "Skew-Tolerant High-Speed Domino Logic", IEEE International Symposium on Circuits and Systems, vol.4 pp.154-157, 2001.
5. S.O. Jung, K.W. Kim, and S.M. Kang "Noise Constrained Power Optimization for Dual Vt Domino Logic", IEEE International Symposium on Circuits and Systems, vol.4, pp.158-161, 2001
6. S.O. Jung, K.W. Kim, and S.M. Kang "Transistor Sizing for Reliable Domino Logic in Dual Threshold Voltage Technology", Great Lakes Symposium on VLSI, pp.133-138, 2001.
7. G. Yang, S.O. Jung, S.H. Kim, and S.M. Kang "Low Power 2.1GHz 32-bit Carry Lookahead Adder Using Dual Path ALL-N-Logic", accepted to IEEE International Midwest Symposium on Circuits and Systems.
8. K.W. Kim, S.O. Jung, P. Saxena, and S.M. Kang "Coupling Delay Optimization by Temporal Decorrelation Dual Threshold Voltage Technique", ACM/IEEE Design Automation Conference, pp.732-737, 2001.
9. K.W. Kim, S.O. Jung, and S.M. Kang "Coupling-Aware Minimum Delay Optimization for Domino Logic", IEEE International Symposium on Circuits and Systems, vol.5, pp.371-374, 2001.
10. S. M. Yoo, S.O. Jung, and S.M. Kang "Low Cost and High Efficient BIST Scheme with 2-Level LFSR and APTP", IEEE International Symposium on Circuits and Systems, vol.4, pp.154-157, 2001.
11. S. M. Yoo, C. Kim, S.O. Jung, K.H. Baek and S.M. Kang "New Current Mode Sense Amplifier for High Density DRAM and PIM Architectures", IEEE International Symposium on Circuits and Systems, vol.4, pp.938-941, 2001.
12. S. M. Yoo, S.O. Jung, and S.M. Kang "2-Level LFSR Scheme with Asynchronous Test Pattern Transfer for Low Cost and High Efficient Built-In-Self-Test", Great Lakes Symposium on VLSI, pp.93-96, 2001.
13. C. Kim, S.O. Jung, K.H. Baek, S.M. Kang "Parallel Dynamic Logic (PDL) and Speed-enhanced Skewed (SSS) CMOS Logic", IEEE International Symposium on Circuits and Systems, pp.756-759, 2000.
14. K.W. Kim, S.O. Jung, Unni Narayanan, C.L.Lin and S.M. Kang "Cross-Coupling Power Characterization and optimization for Noise-Tolerant Domino Logic Synthesis", IEEE International Symposium on Low Power Electronics and Design, pp.108-113, 2000.