University of California at Santa Cruz, Graduate Studies

Report on Qualifying Examination


Name:  Mark Boyd
Department:  Computer Engineering
Date of Examination:  April 14, 2000

Report of the Committee including details of the voting to pass 
or fail the student:

Mark's proposed work deals with hardware accelerators for solving
the Boolean satisfiability problem.  He has developed a novel 
hardware architecture for solution of the problem and has 
prototyped it in a small FPGA.  His dissertation will further
develop the architecture and provide results from running several 
benchmark problems in a larger implementation based on a 
current-generation high-density FPGA.

The committee unanimously agreed that the problem addressed by 
Mark's dissertation proposal is important and timely; and the 
results obtained so far adequately demonstrate his preparation and
ability to complete the dissertation.  The committee has the 
following specific suggestions:

1.  Mark should study approaches to scale his solution approach 
beyond a single-chip implementation.

2.  Mark should primarily limit the scope of his dissertation to
the hardware system and its application to the satisfiability
problem itself, and de-emphasize potential applications of the 
system in other areas.

Signatures of Committee Members:   x Pass

Anujan Varma   Tracy Larrabee   Miron Abramovici   Tara Madhyastha