Previous Work

  

Figure 1: Components of a SAT-Solver.

Instance-specific placement and routing of Field-Programmable Gate Array (FPGA).

Evaluate all implications simultaneously in parallel.

ELVIS is entirely devoted to this IMP component,

 

Table 1: Two-Bit Variable Encoding

v	$\overline{v}$	value
0	0	free
0	1	0
1	0	1
1	1	contradiction

 

Previous work implemented an encoding system for implied values represented in the IMP.

  

Figure 2: Literal Implication Logic for the Clause (10+9+8+7+6+5+4+3+2+1) from hole10.

Use of modular, pre-placed components [23,1] reduces the problem to IMP routing alone, still NP-hard.