Next:
Future Work
Up:
A Scalable, Loadable Custom
Previous:
Design Analysis
Comparison to Previous (FPGA-Based) Approaches
Table 2:
Hardware Requirements of Various Satisfiers
Design
Gates
State
Routing
FCCM98
)
CLAUSE
ELVIS
Table 3:
Latency of Various Satisfiers
Design
Logic Levels
Cyc/Imp
Config
FCCM98
(1)
NP-Hard
CLAUSE
(1)
O
(
m
)
NP-Hard
ELVIS
(1)
Next:
Future Work
Up:
A Scalable, Loadable Custom
Previous:
Design Analysis
2000-04-07