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Comparison to Previous (FPGA-Based) Approaches


 
Table 2: Hardware Requirements of Various Satisfiers
Design Gates State Routing
FCCM98 $\Omega(r^{2}m$) $\Theta(n)$ $\Omega(r^{2}m)$
CLAUSE $\Theta(km)$ $\Theta(nm)$ $\Theta(n)$
ELVIS $\Theta(nm)$ $\Theta(nm)$ $\Theta(nm)$
 


 
Table 3: Latency of Various Satisfiers
Design Logic Levels Cyc/Imp Config
FCCM98 $\Omega(\log (km+rm))$ $\Theta$(1) NP-Hard
CLAUSE $\Theta$(1) O(m) NP-Hard
ELVIS $\Theta(\log m)$ $\Theta$(1) $\Theta(nm)$
 


next up previous
Next: Future Work Up: A Scalable, Loadable Custom Previous: Design Analysis

2000-04-07