Books
 

 1. S. S. Sapatnekar and S. M. Kang, Design Automation for Timing-Driven Layout Synthesis, Kluwer Academic Publishers, 1993.

 2. Y. Leblebici and S. M. Kang, Hot-Carrier Reliability of MOS VLSI Circuits, Kluwer Academic Publishers, 1993.

 3. M. Sriram and S. M. Kang, Physical Design for Multichip Modules, Kluwer Academic Publishers, 1994

 4. C. H. Diaz, S. M. Kang, and C. Duvvury, Modeling of Electrical Overstress in Integrated Circuits, Kluwer Academic Publishers, 1994.

 5. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill, 1995.

 6. J. J. Morikuni and S. M. Kang, Computer-Aided Design of Optoelectronic Integrated Circuits and Systems, Prentice-Hall, 1996.

 7. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill, Second Ed., 1999.

 8. Y.-K. Cheng, C.-H. Tsai, C.-C. Teng and S. M. Kang, Electrothermal Analysis of VLSI Systems , Kluwer Academics, June 2000.

 9. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design , McGraw-Hill, Third Ed., 2002.

  Chapters in Books

1. S. M. Kang and H. Y. Chen, "Circuit Optimization for CMOS VLSI," book chapter, Advances in Computer-Aided Engineering Design, JAI Press, Inc., 1990, pp. 107-157.

2. P. Gee, M. Y. Wu, I. N. Hajj, S. M. Kang, and W. Shu, "Automatic Circuit Synthesis Using Switching Network Logic and Metal-Metal Matrix Layout," book chapter, Advances in Computer-Aided Engineering Design, JAI Press, Inc., 1990, pp. 57-105.

3. S. M. Kang and M. Sriram, "Binary Formulations for Placement and Routing Problems," book chapter, pp. 25-68, Algorithmic Aspects of VLSI Layout (Ed. M. Sarrafzadeh and D. T. Lee), World Scientific, 1994

4. S. M. Kang and A. Dharchoudhury, "Modeling of Circuit Performances," book chapter, pp. 1375-1391, The Circuits and Filters Handbook, CRC/IEEE Press, 1995.

5. Chulwoo Kim and Sung-Mo (Steve) Kang, "Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chips (SoCs)," book chapter, pp. 151-179, Power Aware Design Methodologies, Kluwer Academic Publishers, 2002.

6. K. W. Kim and Sung-Mo (Steve) Kang, "Signal Integrity Effects in Custom IC and ASIC Designs," Raminderpal Singh (editor), IEEE Press, Piscataway NJ and Wiley-Interscience (John Wiley & Sons, Inc.), New York NY, 2002.