Patents
 

U.S. Patent 4,396,994, Data shifting and rotating apparatus, August 2, 1983

U.S. Patent 5,404,041, Source contact placement for efficient ESD/EOS protection in grounded-substrate MOS ICs, April 4, 1995

U.S. Patent 5,450,267, New ESD/EOS protection circuits for integrated circuits fabricated in advanced n-well CMOS processes, September 12, 1995

U.S. Patent 5,610,774, Optical communications and interconnection networks having optoelectronic switches and direct optical routers, March 11, 1997

U.S. Patent 5,796,638, Methods, apparatus and computer program products for synthesizing integrated ircuits with electrostatic discharge capability and correcting ground rules faults therein, August 18, 1998.

U.S. Patent 5,923,656, Scalable broadband input-queued ATM switch including weight driven cell scheduler, July 13, 1999.

U.S. Patent 6,624,665B2, CMOS Skewed Static Logic and Method of Synthesis, Sep 23, 2003.

U.S. Patent 6,759,873, Reverse Biasing Logic Circuit, July 6, 2004.

U.S. Patent 6,784,694B, CMOS Sequential Logic Configuration for an Double-Edge Triggered Flip-Flop, Apr 18, 2002 (Aug 31, 2004)

U.S. Patent 6,784,707, Delay Locked Loop Clock Generator, Aug 31, 2004.

U.S. Patent 6,974,903, CMOS Parallel Dynamic Logic and Speed Enhance Static Logic, Sep 21, 2004.

U.S. Patent 6,900,690, Low Power High Performance Integrated Circuit Architectures and Related Methods.

U.S. Patent 6,946,901, Low-Power High-Performance Integrated Circuits and Related Methods, Sept. 20, 2005.

U.S. Patent 6,977,528, Event Driven Dynamic Logic for Reducing Power Consumption, December 20, 2005

U.S. Patent 6,861,911, Self-Regulating Voltage-Controlled Oscillator, March 1, 2005.