|
|
|
|
2005
|
 |
Ge
Yang, Yong Sin Kim, and Sung-Mo Kang, "Current Mode Mulit-Level Simultaneous
Bidirectional I/O Scheme for Chip-to-Chip Communications", IEEE International
Symposium on Circuits and Systems, Vol. 6, pp.5493-5496, May 2005.
|
|
Sangho Shin, Kwyro Lee and
Sung-Mo Kang, "3.48mW 2.4GHz Range Frequency Synthesizer
Architecture with Two-Point Channel Control for Fast Settling
Performance", IEEE International SOC Conference, pp.3-6, Sept.
2005.
|
|
G.
Yang, S. O. Jung, K. H. Baek, S. H. Kim, S. Kim. and S. M. Kang, " A
32-Bit Carry Lookahead Adder Using Dual-Path All-N Logic
", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13,
NO. 8, pp. 992-996, Aug. 2005 .
|
|
Sung-Mo
Kang, " The Future of IT Education and
Research," Proc. of the Hokkaido Information University International
Forum 2005, Ebetsu, Hokkaido, Japan, Oct. 14-15, 2005, pp. 24-31(English), pp.
32-39 (Japanese).
|
|
2004
|
|
G.
Yang, S.-O. Jung, K.-H. Baek, S. H. Kim, S. Kim, and S.-M. Kang, "A Low-Power
1.85 GHz 32-bit Carry Lookahead Adder Using Dual Path All-N-Logic" ISCAS-2004,
to be presented on May 23, Vancouver, Canada.
|
|
G.
Yang, Z. D. Wang, and S.-M. Kang, "Low Power and High Performance Circuit
Techniques for High Fan-in Dynamic Gates" 5th International Symposium on
Quality Electronic Design, March 2004, Page(s): 421-424.
|
|
G.
Yang, Z. D. Wang, and S.-M. Kang, "Leakage-proof Domino Circuit Design for Deep
Sub-100nm Technologies" The International Conference on VLSI Design, January
2004, Page(s): 222-227.
|
|
Jaesik
Lee, Yoonjong Huh, P. Bendix,and Sung-Mo Kang, "Design of ESD power protection
with diode structures for mixed-power supply systems " IEEE Journal of
Solid-State Circuits,Volume: 39, Issue: 1, Jan. 2004, Page(s):260 - 264
|
|
In-Chul
Hwang, Chulwoo Kim,and Sung-Mo Kang, "A CMOS self-regulating VCO with low
supply sensitivity " IEEE Journal of Solid-State Circuits,Volume: 39, Issue: 1,
Jan. 2004, Page(s):42 - 48
|
|
Jinghong
Chen, Sung-Mo (Steve) Kang, Jun Zhou, Chang Liu, and Jose E. Schutt-Aine,
"Reduced-Order Modeling of Nonlimear MEMS Devices With Taylor-Series Exapnsion
and Arnoldi Approach," Journal of Electromechanical Systems, vol. 13, no. 3,
pp. 441-451, June 2004.
|
|
G.
Yang, Z. D. Wang, and S.-M. Kang, "Gate Leakage Tolerant Circuits In Deep
Sub-100nm CMOS Technologies" submitted to the Institute of Physics (UK) special
issue "Nanotechnology"
|
|
S.
O. Jung, K. W. Kim and S. M. Kang, "Low Swing Clock Domino Logic with Dual
Supply Voltage," submitted to IEEE Trans. on VLSI.
|
|
Shu
Wu and S. M. Kang " Modeling and simulation of Metal-Semiconductor-Metal
photodetector using VHDL-AMS", IEEE proceeding of BMAS 04', October 21-22,
2004, San Jose, CA
|
|
2003
|
|
Yong
Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim and Sung-Mo Kang, "Multiple
Trigonometric Approximation of Sine-Amplitude for High Speed Direct Digital
Frequency Synthesizers," VLSI 2003 symposium, Bombay, India, Jan.
2003,Page(s):261-265.
|
|
Seong-Ook
Jung, Kiwook Kim and Sung-Mo Kang, "Timing Constraints for Domino Logic Gates
with Timing-Dependent Keepers," IEEE Transactions on CAD, vol. 22, no. 1, Jan.
2003, Page(s): 96-104.
|
|
J.
Lee, K-W. Kim, Y. Huh, P. Bendix and Sung-Mo Kang, " Chip-Level Charged-Device
Modeling and Simulation in CMOS Integrated Circuits," IEEE Transactions on CAD,
vol. 22, no. 1, Jan. 2003, Page(s): 67-81.
|
|
C.
Kim, K. W. Kim, and S. M. Kang, "Energy Efficient Skewed Static Logic Design
with Dual Vt," IEEE Trans. on VLSI, vol. 11, no. 1, Feb. 2003, Page(s): 64-70.
|
|
K.
W. Kim, S. O. Jung, U. Narayanan, C. L. Liu, and S. M. Kang, "Noise-Aware
Interconnect Power Optimization in Domino Logic Synthesis," IEEE Trans. on
VLSI, vol. 11, no. 1, Feb. 2003, Page(s): 79-89.
|
|
S.
Wu and Sung-Mo Kang, "Modeling and Time Domain Simulation of VCSEL using
VHDL-AMS," Southwest Symposium on Mixed-Signal Design, May 2003, Page(s):170 -
174.
|
|
Q.
Wang and Sung-Mo Kang, "An Optimal Design of Leak-Proof SRAM Cell Using MCDM
Method," SPIE's International Syposium on Microtechnologies for the New
Millennium, May 19-21, 2003, Gran Canaria, Spain, Volume 5117, Page(s):478-484.
|
|
K.
H. Baek, M.-J. Choe, and S. M. Kang, "An Efficient Calibration Technique for
Systematic Current-Mismatch of D/A Converters," International Symposium on
VLSI, 2003, Page(s): 80-84.
|
|
K.
H. Baek, M.-J. Choe, E. Merlo and S. M. Kang, "Addressing a High-Speed D/A
Converter Design for Mixed-Mode VLSI Systems," IEEE Southwest Symposium on
Mixed-Signal Design (SSMSD), 2003, Page(s):21-26.
|
|
K.
H. Baek, M.-J. Choe, E. Merlo and S. M. Kang, "1-GS/s, 12-Bit SiGe BiCMOS D/A
Converter for High-Speed DDFS," ISCAS 2003, May 25-28,2003, Bangkok, Thailand,
Volume 1, Page(s):901-904.
|
|
Jinghong
Chen, Jun Zou, Chang Liu, Jose E. Schutt-Aine and Sung-Mo Kang, "Design and
Modeling of a Micromachined High-Q Tunable Capacitor With Large Tuning Range
and a Vertical Planar Spiral Inductor,"IEEE Transactions on Electron Device,
VOL. 50, NO. 3, MARCH 2003, Page(s):730-739.
|
|
Ki-Wook
Kim, Seong-Ook Jung, P. Saxena, C. L. Liu and S. M. Kang "Coupling Delay
Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique,"
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Volume: 11 ,
Issue: 5 , Oct. 2003 Page(s):879-887.
|
|
K.
W. Kim, S. O. Jung, T. W. Kim and S. M. Kang, "Minimum Delay Optimization for
Domino Logic Circuits - A Coupling-Aware Approach," ACM Trans. on Design
Automation of Electronic Systems, Volume: 8(2), 2003, Page(s): 202-213.
|
|
G.
Yang and S.-M. Kang, "A New Domino Failure Mechanism in Deep Sub-100nm
Technologies and Its Solution" SPIE International Symposium on
Microelectronics: Design, Technology, and Packaging, December 2003, Proceedings
of SPIE Vol. 5274, Page(s): 70-76.
|
|
S.-M.
Kang and G. Yang, "Gate Leakage Tolerant Circuits In Deep Sub-100nm CMOS
Technologies" Invited paper, SPIE International Symposium on Microelectronics:
Design, Technology, and Packaging, December 2003, Proceedings of SPIE Vol.
5274, Page(s): 56-66.
|
|
S.-M.
Kang, "Elements of Low Power Design for Integrated Systems" Invited paper, IEEE
International Symp. On Power Electronics and Design (ISPLED), Aug. 254-27,
2003, Seoul, Korea., Page(s): 205-210.
|
|
2002
|
|
E.
Conforti, A. C. Bordonalli, S. H. Ho, and S.M. Kang, "Carrier Reuse with Gain
Compression and Feed-Forward Optical Amplifiers," IEEE Trans. on Microwave
Theory and Techniques. vol. 50, issue 1, Jan. 2002. Page(s): 77-81.
|
|
K.
W. Kim, T. W. Kim, C. L. Liu, and S. M. Kang, "Domino Logic Synthesis Based on
Implication Graph," IEEE Trans. on Comput.-Aided Des, vol.21 no.2 Feb. 2002,
Page(s): 232-240.
|
|
Inchul
Hwang and Sung-Mo(Steve) Kang, "A Self-Regulating VCO with Supply Sensitivity
<0.15%-delay/1%-supply," IEEE International Solid-State Circuits Conf, San
Francisco, CA, Feb.3-7, 2002, Page(s):140-141.>
|
|
Chulwoo
Kim, Inchul Hwang and Sung-Mo(Steve) Kang, "Low-Power Small-Area ?.28ps Jitter
1GHz DLL-Based Clock Generator," IEEE International Solid-State Circuits Conf.,
San Francisco, CA, Feb.3-7, 2002, Page(s):142-143.
|
|
Seong-Ook
Jung, Ki-Wook Kim, and Sung-Mo (Steve) Kang, "Dual Threshold Voltage Domino
Logic Synthesis with Noise and Power Constraint," to appear in Design,
Automation and Test in Europe (DATE), Mar. 2002, Page(s):260-265.
|
|
K.
W. Kim, T. W. Kim, T. T. Hwang, S. M. Kang, and C. L. Liu, "Logic
Transformation for Low Power Synthesis," ACM Trans. on Des. Automat. of
Electronic Syst. (TODAES), vol. 7, no. 2, Apr. 2002, Page(s):1-19.
|
|
C.
Kim, S. O. Jung, K. H. Baek, and S. M. Kang, "High-Speed CMOS Circuits with
Parallel Dynamic Logic and Speed-Enhanced Skewed Static Logic," IEEE Trans. on
Circuits and Syst. vol. 49, issue 6, Jun. 2002, Page(s): 434-439
|
|
Jinghong
Chen, Jun Zhou, Chang Liu and Sung-Mo(Steve) Kang, "Development of a MEMs
Vertical Planar Coil Inductor," Fifth International Conf. on Modeling and
Simulation of Microsystems, April.22-25, 2002, San Juan, Puerto Rico, Page(s):
344-347.
|
|
Seong-Ook
Jung and Sung-Mo(Steve) Kang, "Skew-Tolerant High Performance Domino Logic,"
ISVLSI, Pittsburgh, Pennsylvania, 25-26, April, 2002, Page(s): 41-46.
|
|
Kwang-Hyun
Baek, Myung-Jun Choe, and Sung-Mo(Steve) Kang, "A Low-Voltage High-Speed BICMOS
Current Switch With Enhanced-Spectral Performance," ISCAS, May 2002, Arizona,
Page(s): 53-56.
|
|
R.
K. Grube, Qi Wang and Sung-Mo(Steve) Kang, "Design Limitations in Deep
Sub-0.1μm CMOS SRAM Circuits for High-Performance On-Chip Cache
Applications," IEEE Great Lakes Symposium on VLSI, April 18-20, 2002, Page(s):
94-97.
|
|
Jaesik
Lee, Ki-Wook Kim, and Sung-Mo Kang, "VeriCDF: A New Verification Methodology
for Charged Device Failures," ACM/IEEE Design Automation Conf., New Orleans,
LA, June 2002, Page(s): 874-879.
|
|
Seong-Ook
Jung, Kiwook Kim, and Sung-Mo Kang, "Low-Swing Clock Domino Logic Incorporating
Dual Supply and Dual Threshold Voltages," ACM/IEEE Design Automation Conf., New
Orleans, LA, June 10-14, 2002, Page(s): 467-472.
|
|
Chulwoo
Kim, and Sung-Mo Kang, "A low-swing clock double-edge triggered flip-flop,"
IEEE Journal of Solid-State Circuits, Volume 37 Issue 5, May 2002, Page(s):
648-652
|
|
Ge
Yang, Seong-Ook Jung, Soo Hwan Kim and Sung-Mo Kang, "A Low-Power 2.1 GHz
32-bit Carry Lookahead Adder Using Dual Path All-N-Logic," IEEE International
Midwest Symposium on Circuits and Systems, August, 4-7, 2002, Tulsa, Oklahoma.
|
|
S.
O. Jung, K. W. Kim, and S. M. Kang, "Noise Constrained Power Optimization for
Dual Vt Domino Logic," IEEE Trans. on VLSI, vol. 10, no. 5, Page(s): 532-541,
Oct. 2002.
|
|
Chulwoo
Kim, Inchul Hwang and Sung-Mo(Steve) Kang, "Low-Power Small-Area ?.28ps Jitter
1GHz DLL-Based Clock Generator," IEEE Journal of Solid-State Circuits, Volume
37, no.11 November 2002, Page(s): 1414-1420
|
|
2001
|
|
J.
Chen, J. Zou, S. M. Kang, and C. Liu, "Electro-Mechanical and Microwave
S-parameter Properties of a Wide-Tuning Range MEMS Tunable Capacitor," IEEE
Int. Conf. on Modeling and Simulation of Microsystems, Hilton Heal Island, SC,
March 19-21, 2001.
|
|
S.
O. Jung, K. W. Kim, and S. M. Kang, "Transistor Sizing for Reliable Domino
Logic Design in Dual Threshold Voltage Technologies," ACM 11th Great Lakes
Symp. on VLSI (GLSVLSI2001), West Lafayette, Indiana, March 22-23, 2001.
|
|
S.
M. Yoo, S. O. Jung, and S. M. Kang, "2-Level LFSR scheme with Asynchronous Test
Pattern Transfer for Low Cost and High Efficiency Built-In-Self-Test," ACM 11th
Great Lakes Symp. on VLSI (GLSVLSI2001), West Lafayette, Indiana, March 22-23,
2001.
|
|
S.
O. Jung, K. W. Kim, and S. M. Kang, "Noise Constrained Power Optimization for
Dual Vt Domino Logic," IEEE Int. Symp. on Circuits and Syst. (ISCAS'01),
Sydney, Australia, May 6-9, 2001. vol.4, Page(s): 158-161.
|
|
J.
Chen and S. M. Kang, "Model-Order Reduction of Nonlinear MEMS Devices Through
Arclength-Based Karhunen-Loeve Decomposition," IEEE Int. Symp. on Circuits and
Syst. (ISCAS'01), Sydney, Australia, May 6-9, 2001. vol.3, Page(s):457-460.
|
|
S.
M. Yoo, C. W. Kim, S. O. Jung, K. H. Baek, and S. M. Kang, "New Current-mode
Sense Amplifier for High Density DRAM and PIM Architectures," IEEE Int. Symp.
on Circuits and Syst. (ISCAS'01), Sydney, Australia, May 6-9, 2001. vol.4,
Page(s):938-941.
|
|
S.
M. Yoo, S. O. Jung, and S. M. Kang, "Low Cost and High Efficinet BIST Scheme
with 2-Level LFSR and APTP," IEEE Int. Symp. on Circuits and Syst. (ISCAS'01),
Sydney, Australia, May 6-9, 2001. vol.4, Page(s):1-4.
|
|
S.
O. Jung, S. M. Yoo, K. W. Kim, and S. M. Kang, "Skew-Tolerant High-Speed (STHS)
Domino Logic," IEEE Int. Symp. on Circuits and Syst. (ISCAS'01), Sydney,
Australia, May 6-9, 2001. vol.4, Page(s):154-157.
|
|
C.
Kim and S. M. Kang, "A Low-Power Reduced Swing Single Clock Flip-Flop," IEEE
Int. Symp. on Circuits and Syst. (ISCAS'01), Sydney, Australia, May 6-9, 2001.
vol.4, Page(s):806-809.
|
|
Q.
Li, Y. J. Huh, J. W. Chen, P. Bendix, and S. M. Kang, "Full Chip ESD Design
Rule Checking," IEEE Int. Symp. on Circuits and Syst. (ISCAS'01), Sydney,
Australia, May 6-9, 2001. vol.5, Page(s):503-506;
|
|
Q.
Li, Y. J. Huh, J. W. Chen, P. Bendix, and S. M. Kang, "ESD Design Rule
Checker," IEEE Int. Symp. on Circuits and Syst. (ISCAS'01), Sydney, Australia,
May 6-9, 2001. vol.5, Page(s):499-502.
|
|
Q.
Li and S. M. Kang, "Efficient Algorithms for Polygon to Trapezoid-to-Simple
Polygon Recomposition for Resistance Extraction," IEEE Int. Symp. on Circuits
and Syst. (ISCAS'01), Sydney, Australia, May 6-9, 2001. vol.5, Page(s):495-498.
|
|
C.
Kim, K. W. Kim, and S. M. Kang, "Energy Efficient Skewed Static Logic Design
with Dual Vt," IEEE Int. Symp. on Circuits and Syst. (ISCAS'01), Sydney,
Australia, May 6-9, 2001. vol.4, Page(s):882-885.
|
|
K.
W. Kim, S. O. Jung, and S. M. Kang, "Coupling-Aware Minimum Delay Optimization
for Domino Logic Circuits," IEEE Int. Symp. on Circuits and Syst.(ISCAS'01),
Sydney, Australia, May 6-9, 2001. vol.5, Page(s):371-374.
|
|
K.
W. Kim, S. O. Jung, T. W. Kim and S. M. Kang, "Coupling-Aware Minimum Delay
Optimization for Domino Logic Circuits," IEEE Electronics Letters, 2001,
Page(s): 813-814.
|
|
J.
Lee, Y. Huh, P. Bendix, and S. M. Kang, "Design-for-ESD-Reliability in
High-Frequency I/O Interfaces in Deep-Submicron CMOS Technology," IEEE Int.
Symp. on Circuits and Syst.(ISCAS'01), Sydney, Australia, May 6-9, 2001. vol.4,
Page(s):746-749.
|
|
I.
C. Goknar, H. Kutuk, and S. M. Kang, "MOMCO: Method of Moment Components for
Passive Model Order Reduction of RLCG Interconnects," IEEE Trans. on Circuits
and Syst., Part I, Vol.48, No.4, April 2001, Page(s):459-474
|
|
C.
Kim and S. M. Kang, "A Low-Swing Clock Double-Edge Triggered Flip-Flop," IEEE
Symp. on VLSI Circuits, 2001, June 2001, Page(s):183-186.
|
|
Ki-Wook
Kim, Seong-Ook Jung, P. Saxena, C. L. Liu and S. M. Kang "Coupling Delay
Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique,"
IEEE Des. Automat Conf.(DAC), Las Vegas, June 2001, Page(s):732-737.
|
|
In-Chul
Hwang and Sung-Mo(Steve) Kang "Differential Pass-Transistor Clocked Flip-flop,"
Electronics Letters, Vol.37, No.12, June 2001, Page(s):732-734
|
|
Sung-Mo(Steve)
Kang and Seung-Moon Yoo (plenary talk) "Circuit Solutions for Overcoming
Ultra-deep Submicron CMOS Leakage Currents, Noises and Power Consumption,"
Proc. of the International Technical Conf. on Circuits, Systems, Computers and
Communications(ITC-CSCC), July 10-12, 2001, Tokushima, Japan, Page(s):1-4
|
|
Jaesik
Lee, Yoonjong Huh and Peter Bendix, Sung-Mo(Steve) Kang "Understanding and
Addressing the Noise Induced by Electrostatic Discharge in Multiple Power
Supply Systems," Proc. of the International Conf. on Computer Design(ICCD),
Sep. 24-26, 2001, Austin, Texas, Page(s):406-411.
|
|
Jaesik
Lee, Yoonjong Huh, Peter Bendix, Sung-Mo(Steve) Kang "Noise-Aware Design for
ESD Reliability in Mixed-Signal Integrated Circuits," 2001 IEEE Int. ASIC/SOC
Conference Proceedings. 14th IEEE Annual International, 2001, Arlington, VA.
Page(s): 437-441.
|
|
Ki-Wook
Kim, Sung-Mo(Steve) Kang "Crosstalk Noise Minimization in Domino Logic Design,"
IEEE tran. Computer-Aided Design of Integrated Circuits and Systems. Vol.20.
No.9. Sep. 2001. Page(s):1091-1100.
|
|
Jinghong
Chen and Sung-Mo(Steve) Kang "Dynamic Macromodeling of MEMS Mirror Devices,"
IEEE International Electron Device Meeting(IEDM), Washington, DC, Dec. 2001,
Page(s):41.5.1-41.5.4.
|
|
Kwang-Hyun Baek, Myung-Jun Choe, Celso
Souza, and Sung-Mo(Steve) Kang "A Low Glitch SiGe BiCMOS Current Switch for
High Performance D/A Converters," 44th Midwest Symposium on Circuits and
Systems, Page(s):606-609, Aug. 2001.
|
|
2000
|
|
D.
Chen, E. Rosenbaum, and S. M. Kang, "Interconnect Thermal Modeling for Accurate
Simulation of Circuit Timing and Reliability," IEEE Trans. on Comput.-Aided
Des., vol. 19, no. 2, Page(s): 197-205, February 2000.
|
|
C.
H. Tsai and S. M. Kang, "Cell-Level Placement for Improving Substrate Thermal
Distribution," IEEE Trans. on Comput.-Aided Des., vol. 19, no. 2, Page(s):
253-266, February 2000.
|
|
C.
H. Tsai and S. M. Kang, "Efficient Transient Electrothermal Simulation by
Reduced-Order Substrate Thermal Modeling," IEEE Southwest Symp. on Mixed-Signal
Des., San Diego, CA, February 27-29, 2000, Page(s): 185-190.
|
|
Q.
Li and S. M. Kang, "Technology Independent Arbitrary Device Extractor," IEEE
Great Lakes VLSI Symp., Evanston, IL, March 2-4, 2000, Page(s): 143-146.
|
|
Q.
Li and S. M. Kang, "Efficient Algorithms for Polygon to Trapezoid Decomposition
and Trapezoid Corner Stitching," IEEE Great Lakes VLSI Symp., Evanston, IL,
March 2-4, 2000, Page(s): 183-188.
|
|
J.
H. Chen and S. M. Kang, "Techniques for Coupled Circuit and Micromechanical
Simulation," Int. Symp. on Modeling and Simulation of Microsyst. Conf., San
Diego, CA, March 27-29, 2000, Page(s): 213-216.
|
|
K.
H. Baek, K. W. Kim, and S. M. Kang, "EXODUS: An Inter-Module Bus-Encoding
Scheme for System-On-A-Chip," IEE Electronic Lett., vol. 36, no. 7, Page(s):
615-617, March 2000.
|
|
S.
O. Jung and S. M. Kang, "Modular Charge Recycling Pass Transistor Logic
(MCRPL)," IEE Electronic Lett., vol. 36, no. 5, Page(s): 404-405, March 2000.
|
|
J.
Chen and S. M. Kang, "An Algorithm for Automatic Model Reduction of Nonlinear
MEMS Devices," IEEE Int. Symp. on Circuits and Syst., Geneva, Switzerland, May
28-31, 2000, Page(s): 445-448, vol. 2.
|
|
C.
Kim, S. O. Jung, K. H. Baek, and S. M. Kang, "Parallel Dynamic Logic (PDL) and
Speed-Enhanced Skewed Static (SSS) Logic," IEEE Int. Symp. on Circuits and
Syst., Geneva, Switzerland, May 28-31, 2000, Page(s): 756-759.
|
|
S.-M.
Yoo and S.-M. Kang, "New High Performance Sub-1V Circuit Technique with Reduced
Standby Current and Robust Data Holding," IEEE Int. Symp. on Circuits and
Syst., Geneva, Switzerland, May 28-31, 2000, Page(s): 65-68, vol. 4.
|
|
K.
W. Kim, U. Narayanan, and S. M. Kang, "Domino Logic Synthesis Minimizing
Crosstalk," IEEE Des. Automat. Conf. (DAC), Los Angeles, CA, June 5-9, 2000,
Page(s): 280-285.
|
|
C.
H. Tsai and S. M. Kang, "Fast Temperature Calculation for Transient
Electrothermal Simulation by Mixed Frequency/Time Domain Thermal Model
Reduction," IEEE Des. Automat. Conf. (DAC), Los Angeles, CA, June 5-9, 2000,
Page(s): 750-755.
|
|
S.
M. Yoo, C. Kim, S. O. Jung, K. H. Baek, and S. M. Kang, "New Current Sense
Amplifier for High Density DRAMs and PIM Architecture," SEMICON West 2000
(Poster), San Francisco, CA, July 10-12, 2000.
|
|
K.
W. Kim, S. O. Jung, U. Narayana, C. L. Liu, and S. M. Kang, "Noise-Aware Power
Optimization for On-Chip Interconnect," Int. Symp. on Low Power Electronic and
Des., Rapallo, Italy, July 26-27, 2000, Page(s): 108-113.
|
|
J.
Chen and S. M. Kang, "Model-Order Reduction of Weakly Nonlinear Systems with
Taylor Series Expansion and Arnoldi Approach," IEEE 43rd Midwest Symp. on
Circuits and Syst. (MWSCAS 2000), Lansing, MI, August 8-11, 2000, Page(s):
248-251.
|
|
K.
H. Baek, K. W. Kim, and S. M. Kang, "A Low Energy Encoding Technique for
Reduction of Coupling Effects in SoC Interconnects," IEEE 43rd Midwest Symp. on
Circuits and Syst. (MWSCAS 2000), Lansing, MI, August 8-11, 2000, Page(s):
80-83.
|
|
J.
Moorman, J. Lockwood, and S. M. Kang, "Real-Time Prioritized Call Admission
Control in a Base Station Scheduler," ACM Wowmom, Boston, MA, August 2000,
Page(s): 28-37.
|
|
C.
Kim, S. M. Yoo, and S. M. Kang, "Low Power Adiabatic Computing with NMOS Energy
Recovery Logic," IEE Electronics Lett., vol. 36, no. 16, Page(s): 1349-1350,
August 2000.
|
|
C.
Kim, J. Lee, K. H. Baek, and S. M. Kang, "Low-Power Skewed Static Logic with
Topology-dependent Dual Vt," 2000 13th Annual IEEE Int. ASIC/SOC Conf.,
Washington, DC, September 13-15, 2000, Page(s): 310-314.
|
|
C.
Kim, J. Lee, K. H. Baek, E. Martina, S. M. Kang, "High-Performance, Low-Power,
Skewed Static Logic in Very Deep-Submicron (VDSM) Technology," IEEE Int. Conf.
on Comput. Des. 2000, Austin, TX, September 17-20, 2000, Page(s): 59-64.
|
|
S.
Joshi, P. Juliano, E. Rosenbaum, G. Kaatz and S. M. Kang, "ESD Protection for
BiCMOS Circuits," Proc. of the 2000 IEEE Bipolar/BiCMOS Circuits and Technol.
Mtg., Minneapolis, MN, September 24-26, 2000, Page(s): 218-221.
|
|
J.
S. Lee, Y. J. Huh, P. Bendix, and S. M. Kang, "Chip-Level Simulation for CDM
Failures in Multi-Power ICs," EOS/ESD Symp., Anaheim, CA, September 26-28, 2000
(Best Student Paper Award).
|
|
Y.-K.
Cheng and S. M. Kang, "A Temperature-Aware Simulation Environment for Reliable
ULSI Chip Design," IEEE Trans. on Comput.-Aided Des., Page(s): 1211-1220,
October 2000.
|
|
K.
W. Kim, K. H. Baek, N. Shanbhag, C. L. Liu, and S. M. Kang, "Coupling-Driven
Signal Encoding Schemes for Low-Power Interface Design," IEEE Int. Conf. on
Comput.-Aided Des. (ICCAD 2000), San Jose, CA, November 5-9, 2000, Page(s):
318-321.
|
|
S.
Bucheli, J. R. Moorman, J. W. Lockwood, and S. M. Kang, "Compensation Modeling
for QoS Support on a Wireless Network," Globcomm 2000, San Francisco, CA,
November 2000, Page(s): 198-202, vol. 1.
|
|
J.
Zou, C. Liu, J. Chen, and S. M. Kang, "Development of a Wide Tuning Range MEMS
Tunable Capacitor for Wireless Communication Systems," IEEE IEDM '2000,
Page(s): 403-406.
|
|
J.
Chen and S. M. Kang, "Computer-Aided Design of Mixed-Technology VLSI Systems,"
IEEE Asian Pacific Conf. On Circuits and Systems, Tianjin, China, December
2000.
|
|
|
