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The Kestrel processing element layout features an
<A HREF="multiplier.html">8x8 multiplier</a>, a
<A HREF="sram.html">256x8 local memory</a>, a
<A HREF="registers.html">32x8 3-port shared register bank</a>,
and a <A HREF="datapath.html">datapath</A> featuring an alu,
comparator, minimizer and bit shifter. We have completed a
<a href="prototype.html">2-PE prototype</a>, a <a
href="k64.html">64-PE chip</a> with 1.4 million transistors and a
<a href="board.html">PCI Board</a>.
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