Final grades for the lab portion of the class will be posted later (perhaps tonight).
All grade disputes (lecture and lab) MUST be resolved by 11 pm on Monday, June 18th. There are no extensions possible beyond this time, as grades need to be submitted the next morning.
If you want to dispute your grade, I would recommend that you first use the spreadsheet on the class web page to see where you actually stand in terms of points and how close your are to the grade you want.
If your dispute is specifically related to the final exam, you will want to review the answer key and see how close your actual answers on the exam were to the answer key.
The deadline for completing the survey is *Friday, June 15th*, and the winner of the raffle will be announced at graduation.
The survey can be found at: http://www.soe.ucsc.edu/advising/undergraduate/exit.html
Two pages of notes are allowed on the final. (8.5" x 11" paper, both sides)
Additional office hours are available next week if you happen to be near Santa Clara University. I'll be there on Tuesday (6/12) from 3:15 pm to 4:45 pm. My office is at Cesar Chavez 124B. It's a trailer building located just off of Franklin Street. There is plenty of parking along that street or on nearby side streets. A map of the university can be found here.
In addition to bringing the simulation files to office hours, you'll also need to bring printouts of the circuit and all simulation results (just in case there are issues loading/running the program).
I've added a link below to a pdf file (via Wikipedia) on the Widlar current source. They do a pretty good treatment of the output resistance calculation (using a small signal model). It is worth reviewing, in my opinion. A similar pdf file can also be found on the Wilson current source (which will be covered on Tuesday).
For the common-emitter simulations, be careful about what you define as input. In class, the gain was only 50 because the input was defined as "Vs". If you define the input as the voltage drop across the 5k resistor, you will get results that match those in the textbook.
Homework problems for Chapters 5 and 7 have been posted below.
You will be allowed to use one page of notes on the midterm exam. (8.5" x 11" sheet of paper, both sides)
There is also a text file which contains some notes and tips on using the program. You may find this program useful in checking the answers to some of your homework problems.
If you have issues using the design I downloaded, you'll need to bring your computer (assuming it's a laptop) to class. Otherwise, you'll have to install some sort of program (like VNC) so that the problem can be debugged via the internet. (alternatively, just go through the content in the Tront book and trying using the concepts on one of the circuits you see in the textbook)
A job fair will be held by the UCSC Career Center next week. More details can be found here.
Lecture notes for this week have been added to the class web page below.
A revised syllabus, indicating how much homework counts for your final grade will be posted shortly.
Homework
problems and solutions for Chapter 1
Homework
problems and solutions for Chapter 2 (due Tuesday, April 17th)
Homework
problems and solutions for Chapter 3 (due Tuesday, April 24th) (last updated
4/17)
Homework
problems and solutions for Chapter 4
Midterm solutions
Homework
problems and solutions for Chapter 5 (due Thursday, May 10th)
Homework
problems and solutions for Chapter 7 (due Tuesday, May 22nd)
Homework
problems and solutions for Chapter 8 (due Tuesday, May 29th)
Homework
problems and solutions for Chapters 3, 4, 6 (Digital Logic) and 9 (Feedback)
Extra credit
assignment
Some tips on preparing for the final exam.
Final exam solutions
Syllabus
(last updated 4/22)
Discussion
forum for the course
Materials for the EE 171/L lab section.
A spreadsheet you can use to determine your course grade. (last updated 6/17)
Class schedule (last updated 5/6)
Lecture 1
(Introduction/Amplifiers, 4/3/07)
Lecture 2
(Operational Amplifiers, 4/5/07)
Lectures 3 and 4
(Op Amp Imperfections, 4/10/07 and 4/12/07)
Lecture 5
(Diodes, 4/17/07)
Lecture 6
(Bipolar Junction Transistors, 4/19/07)
Lecture 7
(BJT Large Circuit Models, 4/24/07)
Lecture 8
(BJT Small Circuit Models, 4/26/07) (slide 4 corrected, 5/8)
Lectures 9 and
11
(MOS Transistors, 5/1/07 and 5/8/07) (slide 15 corrected and slide 16
updated, 5/8)
Lecture 12
(Current Sources, 5/10/07)
Lectures 13
and 14 (Differential amplifiers, 5/15/07 and 5/17/07)
Lecture 15 (High
Frequency Analysis I, 5/22/07) (slide 17 corrected, 5/20...slides 5, 6,
and 8 corrected, 5/24)
Lectures 16
and 17 (High
Frequency Analysis II, 5/24/07 and 5/29/07)
Lectures 18
and 19 (Digital Logic, 5/31/07 and 6/5/07) (slides 14, 15, and 16
corrected, 5/31)
Lectures 19
and 20 (Feedback, 6/5/07 and 6/7/07)
An online website for the textbook
Calculation of the output
resistance for a Wildar current source.
OrCAD design files:
Last Updated: 3/6/2007.