Coursework:

• 20% Homeworks
• 30% Midterm Exam
• 30% Presentation of 2-3 papers
• 20% Projects (report and presentation)

Topics:

• Technology Mapping
  
  1. Look-up tables
  2. Ashenhurst decomposition & Roth-Karp decomposition
  3. Flow-map
  4. Routability aspects
• Placement
  
  1. Simulated Annealing
  2. Force-directed placement: Conjugate Gradient Method
  3. Placement for Hierarchical FPGAs
  4. Delay calculations, slack
• Routing
  
  1. Negotiation-based routing
  2. Global routing; wire type assignment
  3. Universal switches
• Miscellaneous Issues
  
  1. Retiming
  2. Synthesized optimal placements
  3. Parallelization of FPGA CAD algorithms
  4. IO placement
  5. Interconnect for reconfigurable Multi-FPGA systems

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