General Class Information
- Lecture times: Monday and Wednesday, 5:00-6:45pm
- Class: JBE 156
- Instructor: Jose Renau
Office Hours: Friday, 4:00-6:00 PM
Office: E2 227
- Text book: None. See reading list
- Mailing list: SCOORE Mailing list
Grading
- Paper Reviews: 40%
- Project: 60%
Policy
- No exams, midterms, or homeworks. Grading is based on paper reviews
and project.
Class Description
CMPE221 is an introduction to the latest advances in computer
architecture. Focuses on processor core design. Topics include simultaneous
multithreading, thread level speculation, trace caches, novel out-of-order
mechanisms, and energy-efficient processor core designs.
Final project requires the modification/enhancement of an out-of-order
processor on an FPGA development system. The class project will resemble
real industry projects. Students will work/collaborate on the same cvs
source project. Each group will be in charge of different processor parts.
Examples of projects: Enhancing the branch predictor, support
load-speculation, memory stride prefetchers, support interrupts...
Requirements: To take this class you are required to be knowledgeable of
on computer architecture (cmpe202 or equivalent), and to have some
experience with Verilog and/or VHDL (cmpe125 or equivalent). Concurrent
enrollment in the Lab class is required. Email instructor if you can not
access the lab (Cupertino). No textbook is required.
CMPE221/L (3 credit) consists of weekly two-hour lab session, and 10-15
hours of independent work.
This course consists of two major blocks: Theory and lab. For the lab we
use modelSim, quartus
II, and Symplicity
Pro. We also have several FPGA altera
boards with one of the most modern FPGA chips available (Stratix II).
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