General Class Information

• Lecture times: Tuesday & Thursday, 12-13:45 PM
• Class: JBE 165
• Instructor: Jose Renau
  Office Hours: Friday, 4:00-6:00 PM
  Office: E2 227
• Text book (optional): Verilog Styles for Synthesis of Digital Systems
• Newsgroup: ucsc.class.cmpe126
  Mailing list interface for the newsgroup

Grading

• Homeworks: 42% (8.4% per homework)
• Projects: 58% (5% Interface, 28% RTL Design, 15% RTL Verification, 5% Presentation, 5% Report)

Policy

• Exams are open book. You can bring all the books (no computers) that you want.
• Late policy: 1 minute late, no grade
• Homeworks are done INDIVIDUALLY.