Preparation

Lab work

Simple design entry and simulation of a 2-input AND gate using M3.1i Foundation Tools

1. program manager
2. schematic (gate-level drawing tool)
3. simulation and waveform viewing
4. implementation (map, placement and routing (PAR), bitstream generation (bitgen))
5. download the bitstream to configure the Xilinx chip

The foundation series is very fragile. There are restrictions and limitations. See FAQ below.

1. First, use the Foundation Program Manager to create a new project

This program component manages the different versions of the your project, and interfaces between different components.

Start a new project, give your new project a name e.g. foo.

Select the correct part type (FPGA chip) XC4003EPC84-1 package type and speed, which means FPGA 4003E part PLCC (plastic leadless chip carrier) package with 84 pins, speed grade is 1.

Foundation Manager

2. Next, start schematic drawing tool

Plan ahead, note the number of primary inputs and outputs that you need. (The implementation-correct way of doing this is to add IPAD and IBUF, OPAD and OBUF to the Primary Inputs or Outputs. But the foundation series has its idiosyncrasy: it prefers to use "terminals" so that it would work properly with the functional simulator). For this lab, use "terminals."

Lay down the components and terminals that you need by extracting them from the library. Connect the components, and label the connections (nets).

Save the file.

This drawing is for simulation only. You need to do a few more things (adding buffers, lock down the pins) for actual implementation.

Schematic Drawing for simulation (note that there are no I/O buffers nor I/O pads)

3. Start and run simulation tool

Activate the inputs and observe the outputs. Try all input combinations.

5. Proudly present your drawing and simulation results to your TA.

6. Things to watch for and things NOT to do.

1. Watch the command log, watch for warnings and loadless nets or hanging terminals
2. Watch for unconnected nets. It is easy to create a dangling wire (net) in the schematic editor. For example, if you miss a connection by a couple of pixels, the net will be left unconnected.
3. Maintain only one copy of your drawing. It is a bad idea to have multiple versions of your drawings kept under the same project name. The interface between the schematic editor and the simulator will get confused, and the simulator might pick the incorrect schematic drawing as inputs to the simulation.
4. Often, the color map of the project manager got messed up: the background color becomes black. This is harmless but annoying.
5. If your simulation results weren't what you expected. Go back to the drawing and check.

Documentation.

So just generate a postscript file of the schematic and simulation results and print out to the postscript printer.

Foundation Series FAQ (for future labs):

1. How do I lock the pins down. What does locking the pins down mean ?

   Most of the Xilinx I/O pins are general purpose. So the implementation tool PAR can pick whichever I/O pins it likes to implement your design. This is not so nice after you have hardwired up your Xilinx chip to the switches and LEDs and clocks on the protoboard. So you would like to preserve the same pin assignment during different implementation runs. This is called locking down the pins.

   You can either edit the design.UCF file or use LOC attribute at the IOPADs (terminals) to construct your own pin assignment.

2. Foundation Schematic Editor: What do green net labels mean?

   Answer: A green wire label means that the label is not associated with a net -- it is merely a floating net label. A blue label is a net label which is associated with an actual net.

   Note that bus labels are green -- even when they are associated with an actual bus.

3. How do I add attributes using the Foundation Schematic Editor?

   Answer: Some attributes require both a name and a value to be entered. These include LOC and TNM. For a complete list of Xilinx attributes, refer to Chapter 4 of the Libraries Guide. Follow these steps to add an attribute with a value:

   1. Double-click on the net or symbol you wish to place the attribute on. If it is a net, click on the Attributes button.

   2. In the "Parameter Name" or Parameters -> Name field, enter the name of the attribute (e.g. LOC).

   3. In the "Parameter Description" or Parameters -> Description field, enter the value of the attribute (e.g. P12).

   4. Click the Add button. The attribute will appear in the list box. The number of dots next to the attribute in the list box determines what part of the attribute is displayed on the schematic. Double-clicking on the parameter in the list box will change the number of dots:

   0 dots: Neither the Name nor Description will be displayed. 1 dot : The Description only will be displayed. 2 dots: Both the Name and Description will be displayed.

4. Do not use the Power Symbols (VCC, GND) from the Schematic Editor Toolbar

   Do not use the Power Symbols from the left-hand side of the schematic toolbar. Problems have been seen in the Implementation tools related to using these power symbols in a schematic design.

   When using VCC or GND, you should use the VCC and GND components from the Xilinx Unified Library. These components may be selected from the Symbols Toolbox symbol list.

5. See support.xilinx.com for more bug reports.