1. Referring to the Mealy GUM vending machine discussed in the class. Use D edge-triggered flip-flops.
   1. Present the State table.
   2. Use Gray code for state assignment: S0=00, S1=01, S2=10
   3. Use two bits to encode the inputs: N, D, and E. N=<0,0>, D=<0,1>, and E=<1,1>
   4. Present the Excitation table.
   5. Draw the excitation Karnaugh maps for the next state logic of each D edge-triggered flip-flops.
   6. Derive the output logic.
   7. Derive the excitation equations from the maps.

2. An negative-edge-detector is a finite-state machine with a single input whose output goes low for exactly one clock cycle when the input goes low and stays low until the next clock. We assume that the input changes at a slow enough rate that it does not have two transitions within any single clock period. Notice that the input is unsynchronized , which means you cannot feed the input directly into the state machine. Take this into consideration in your design.
   

   Use D edge-triggered flip-flops.

   1. Determine whether a Moore or a Mealy machine will be the most appropriate for the design.
   2. Draw the state diagram. Highlight the initial (RESET) state.
   3. Present the State table.
   4. Choose a good state encoding to encode the state, be wise.
   5. Present the Excitation table.
   6. Draw the excitation Karnaugh maps for the next state logic of each D edge-triggered flip-flops.
   7. Draw the Karnaugh map for output logic.
   8. Derive the excitation and output equations from the maps.
   9. Present a logic diagram of the implementation of the FSM, check if the logic make sense.

3. Complete the timing diagram for the arbiter that was discussed in class.
   

4. Expand the idea of the two-processor arbiter that was discussed in class: a new arbiter has to process 3 requests R1, R2, and R3 from Processors 1, 2, and 3 respectively. The new arbiter has 3 output signals, G1, G2 and G3. The new arbiter has to be fair. Processor 1 has a small edge over Processor 2, and Processor 2 has a small edge over Processor 3.

   Question: draw a state diagram for the new arbiter. Minimize the number of states. Yes, I want just the state diagram.

5. Complete the timing diagram for the one-hot encoded FSM that was discussed in class. Assuming that each logic gate incurs one delta delay.
   

1. Read chapter 7.4, 8.1, 8.2, 8.3

2. Gray code counter: Design a 3-bit Gray code counter. Let output=state value. Use D edge-triggered flip-flops.
   1. Draw a state diagram. Highlight the initial (RESET) state.
   2. Present a transition table (see pg 471 of text for definition).
   3. Draw the excitation Karnaugh maps for the next state logic of each D edge-triggered flip-flops.
   4. Derive the excitation equations from the maps.

3. Modulo counter: Design a mod 6 binary counter. The constraint is

    output=state values

   Use D edge-triggered flip-flops.
   1. Draw a state diagram. Highlight the initial (RESET) state.
   2. Present a transition table.
   3. Draw the excitation Karnaugh maps for the next state logic of each D edge-triggered flip-flops.
   4. Derive the excitation equations from the maps.

4. Design a counter that output the following sequence repeatedly:

                (54)->(89)->(13)
     

   Let

                output = function(state values)
     

   Use D edge-triggered flip-flops. Represent the output as two Binary-Coded Decimal (BCD) digits, that is 8 bits. For example, (54) is reprsented as <0101 0100> Notice that the counting sequence is short, but the number of output bits is large. Use one-hot encoding for state assignment.
   1. Draw a state diagram. Highlight the initial (RESET) state.
   2. Present a Transition and output table.
   3. Draw the excitation (Karnaugh) maps for the next state logic of each D edge-triggered flip-flops.
   4. Draw the Karnaugh maps for the output logic.
   5. Derive the excitation and output equations from maps.

5. Design a counter that output the following sequence repeatedly:

                (54)->(89)->(13)
     

   Let

                output = state values
     

   Use D edge-triggered flip-flops. Represent the output as two BCD digits, that is 8 bits. Notice that the counting sequence is short, but the number of output bits is large.
   1. Draw a state diagram. Highlight the initial (RESET) state.
   2. Present a Transition table.
   3. Draw the excitation (Karnaugh) maps for the next state logic of each D edge-triggered flip-flops.
   4. Derive the excitation equations from the excitation maps.

6. Do the Mealy finite-state machine (traffic light controller) design for Lab 5. Use D edge-triggered flip-flops.
   1. Draw a state diagram. Highlight the initial (RESET) state.
   2. Present a State/Output table.
   3. (Must) Use one-hot encoding for state assignment.
   4. Present an Excitation table.
   5. Draw the excitation Karnaugh maps for the next state logic of each D edge-triggered flip-flops. (If the number of input variables for your Karnaugh maps is too many, you may do it by inspection.)
   6. Draw the Karnaugh map for output logic.
   7. Derive the excitation equations from the maps.

Assignment 4 : do all 6 problems, due Feb 8, 2000. Solution will be available by then.

1. Read Electrical Circuits Review by Bruce M. Fleischer (.pdf, 85K). Also in appendix of the 1st edition of the Wakerly book.
2. Read Chapter 3.1-3.5, 3.7, 3.9.
3. Three resistors R1, R2, and R3 are connected in parallel. Using the first principles (KCL, KVL, and Ohm's Law) to find the equivalent resistance ( Req ) of these resistors. Please show all your derivations starting from the first principles.
4. Current divider: Show that when two resistors R1 and and R2 are connected in parallel, the resistors divide the total current (sum of the currents in the resistors) proportional to R1/(R1+R2) for R2, and proportional to R2/(R1+R2) for R1.

   Please start from the first principles: KCL, KVL and Ohm's Law.

5. Do problem B.4 (the resistor cube) in Electrical Circuits Review by Bruce M. Fleischer.

   Or A.4 (the resistor cube) in Appendix of the 1st edition of Walkerly's Book. Hint: this is an exercise of KCL, so be tricky, look at the cube carefully, look for symmetry ... use KCL ... current is divided at each junction.

6. (midf99 problem) Given resistors R1, R2, R3 and voltage source VCC. Using the first principles (KCL, KVL, Ohm's Law) to represent VOUT in terms of R1, R2, R3 and VCC.

    

   

    

7. 3.13
8. 3.65

Solution 4

Assignment 3 : Do all 7 problems. Due Jan 27, 2000, 2pm in class.

1. Read Chapter 4.3
2. Do problems in Text 4.13 a,b,c,e; and find both minimal product-of-sums and minimal sum-of-products forms. Skip the "indicate the distinguished 1-cells in each map" part for now.
3. Text 4.49. Do also (supplement to c) f = xy + x'y'
4. Text 4.56
5. Text 4.60 c,d,e; and find both minimal product-of-sums and minimal sum-of-products forms.
6. (Fall 99 final) A 2-bit comparator switching function f receives two 2-bit vectors vec(P) and vec(Q).

           vec(P) = < P_1 P_0 >
   

   representing the magnitude of a positive integer P, and

           vec(Q) = < Q_1 Q_0 >
   

   representing the magnitude of a positive integer Q. The comparator function f produces a 1 output if and only if P is greater than or equal to Q.

   Find the minimal sum-of-products (SOP) form for f using only algebraic simplification technique. Start with the following switching expression and state the switching theorem used in each step of the simplification. The * symbol represents the Boolean AND operation.

      f = P_1*Q_1' + (P_1*Q_1 + P_1'* Q_1')*(P_0 + P_0'*Q_0')
   

7. Text 4.62 e,f.

Solution 3

Assignment 2 : Do all 9 problems. Due Jan 20, 2000, 2pm in class.

1. Read chapter 2.1-2.7,2.8,2.11-12,2.14,2.15
2. Read chapter 4.1
3. Do exercise Text 2.19, but the equation should really be

          [x+y] = ( [x] + [y] ) modulo  2^n
    

4. Do exercise Text 2.22
5. Encode the decimal number 251 in Hamming Code for single-error correction using odd parity. Derive the number of syndrome bits that is needed. Show the encoding (coded message=message+syndrome), step by step.
   Inject an error in position 6 of the code. Remember, according to Richard W. Hamming the left most position is position one. Evaluate the syndrome, and verify that the error indeed can be corrected. Show the error correction, step by step.

6. Suppose that Axioma (A3), (A3'), (A4), (A4), (A5), and (A5') of the switching algebra are being replaced by new binary operators + and . defined by:

            + | 0   1               . | 0   1
           -----------             -----------
            0 | 0   1               0 | 1   1
            1 | 1   0               1 | 1   0
   

   What effect will these changes have on Theorems (T1) to (T5')? Will the Theorems still hold?
   (The formal way of stating the previous questions: Does the binary operators constitute a switch algebra?)
7. Do Text Exercises 4.30
8. Do Text Exercises 4.25, 4.26
9. Do Text Drill Problems 4.5, 4.6

Solution 2

Assignment 1 : Do all 10 problems. Due Jan 13, 2000, 2pm in class. Please show all steps.

1. Read chapter 2.1-2.4.
2. Optional: read ahead chapter 2.5-2.6 if you are comfortable with the material
3. Do exercises Text 2.2a, 2.2f
4. Do exercises Text 2.4e, 2.4j, 2.5g
5. (Midterm Fall99) Convert the following decimal number

       <3485321>
   

   to the radix 2 binary representation (without leading zeroes).
6. Given radix=2, D={0,1,-1}, n=8, and the interpretation rule for a bit vector vec(x) is simply mag(vec(x)). See equation (1) below for the definition of mag(). A value X is currently represented by the bit vector:

            <01010101>
   

   Problem: find a different representation of X.
7. Text 2.10
8. Find the simplest closed-form expression for the following sum to n terms

         5 + 55 + 555 + 5555 + 55555 + .... + ..
   

   all numbers are represented in decimal.
9. Text 2.16
10. (Midterm Fall99)

     

    

     

All labs meet in Baskin Engineering 104. The first lab starts on Jan 10 of the quarter.

There are 7 laboratory assignments for the course.

• Week 10: Mar(13,14) make up and lab final.
• Lab 6: Lab 6 is ready.
• Lab 5: Lab 5 is ready, Two sessions. Traffic-light lab.
• Lab 4 : Lab 4 is ready, Counter lab, one session.
• Lab 3 : Lab 3 is ready. Two sessions (week 5 and week 6 for this lab) PS: Feb 5, I added a paragraph that describes measuring the difference between two signals.
• Lab 2 : 4-bit ALU.
• Lab 1 has three parts: A. fpga-demo board, , B. schematic drawing and simulation and C. Design Implmentation

• Lab Exam, second half of the tenth week.

1. Title
2. Objectives and/or Specifications
3. Methods (steps, techniques) and apparatus,
4. Problems and solutions
5. Results
6. Drawings, Schematics and/or timing diagrams

What we are going to look at.

• Week 1: Number representation, arithmetic, codes, code conversions (2.1-2.7,2.8,2.11-12,2.14,2.15)
• Week 2: Boolean/Switching algebra, minimization, and Karnaugh maps (ch 4)
• Week 3: Basic electronics and logic gates (some of ch 3). You may want to read Electrical Circuits Review by Bruce M. Fleischer (.pdf, 85K). Also in appendix of the 1st edition of the Wakerly book.
• Week 4: Combinational logic design practices (ch 5)
• Week 5: MIDTERM
• Week 6: Sequential logic design, flip-flops
• Week 7: Synchronous Sequential Circuits, Finite State Machines
• Week 8: Sequential logic design, Finite State Machines
• Week 9: Asynchronous sequential design (latches)
• Week 10: Programmable logic devices (PLA, PAL, FPGA)