\begin{thebibliography}{99}
@String{CMUSRC = "SRC-CMU Center for Computer-Aided Design, Dept. of ECE"}
@String{CICC = "Proceedings of the Custom Integrated Circuits Confernce"}
@String{CRC = "Center for Reliable Computing, Depts. of Elect. Eng. and Computer Science"}
@String{IEEETC = "IEEE Transactions on Computers"}
@String{IEEETCAD = "IEEE Transactions on Computer-Aided Design"}
@String{IEEETED = "IEEE Transactions on Electron Devices"}
@String{IEEETCS = "IEEE Transactions on Circuits and Systems"}
@String{IEEEDTC = "IEEE Design and Test of Computers"}
@String{IEEETSM = "IEEE Transactions on Semiconductor Manufacturing"}
@String{JETTA= "Journal of Electronic Testing: Theory and Applications"}
@String{IEEEJSSC= "IEEE Journal of Solid-State Circuits"}
@String{MICRO = "IEEE Micro"}
@String{PrITC ="Proceedings of International Test Conference"}
@String{PrASIC ="Proceedings of IEEE ASIC Conference"}
@String{PrETC ="Proceedings of European Test Conference"}
@String{PrICCAD = "Proceedings of International Conference on Computer-Aided Design"}
@String{PrDAC = "Proceedings of Design Automation Conference"}
@String{PrICCD = "Proceedings of International Conference on Computer Design"}
@String{PrVTS = "Proceedings of VLSI Test Symposium"}
@String{PrFTCS = "Proceedings of Fault Tolerant Computing Symposium"}

@article{68020,
	Title="The Motorola {MC68020}",
	Author="D. MacGregor and D. Mothersole and B. Moyer", 
	Journal=MICRO,
	Year="1984",Month="August",
	Volume="4",Number="4",
	Pages="101-118",
	key="MacGregor"}

@Article{ABOU85
	,key="Aboulhamid"
	,author="E.M. Aboulhamid"
	,title="Efficient Testing and Truth Table Verification of
Unilateral Combinational Iterative Arrays"
	,journal= PrICCAD
	,year="1985",pages="68-70"
	,Annote="Corrects Dias"}

@article{ABRA83,
	Title="A Practical Approach to Fault Simulation and Test Generation for Bridging Faults",
	Author="M. Abramovici and P.R. Menon", 
	Journal=IEEETC,
	Year="1985",Month="July",
	Volume="C-34",Number="7",
	Pages="658-663",
	key="Abramovici"}

@article{ABRA86,
	Title="{SMART} and {FAST}: Test Generation for {VLSI} Scan-Design Circuits",
	Author="M. Abramovici and J.J. Kulikowski and P.R. Menon and D.T. Miller", 
	Journal=IEEEDTC,
	Year="1986",Month="August",
	Volume="3",Number="4",
	Pages="43-54",
	key="Abramovici"}

@Book{ABRA_BOOK,
	Author="M. Abramovici and M.A. Breuer and A.D. Friedman",
	Key="Abramovici",
	Title="Digital Systems Testing and Testable Design",
	Publisher="Computer Science Press",
	Year="1990"}

@Article{ACKE83
	,key="Acken"
	,author="J.M. Acken"
	,title="Testing for Bridging Faults (Shorts) in {CMOS} Circuits"
	,journal= PrDAC
	,year="1983",pages="717-718"
	,Annote="To test bridging output faults, put different values on them"}

@PhDThesis{AckenThesis,
	Author="John M. Acken",
	Title="Deriving Accurate Fault Models",
	School="Stanford University, Department of Electrical Engineering",
	Month="September",
	Year="1988", Key="Acken"}

@Article{ACKE91
	,key="Acken"
	,author="J.M. Acken and S.D. Millman"
	,title="Accurate modeling and simulation of bridging faults"
	,journal= CICC
	,year="1991",pages="17.4.1-17.4.4"}

@Article{ACKE92
	,key="Acken"
	,author="J.M. Acken and S.D. Millman"
	,title="Fault model evolution for diagnosis:  Accuracy vs precision"
	,journal= CICC
	,year="1992"}

@Article{AGAR80
	,key="Agarwal"
	,author="V.K. Agarwal"
	,title="Multiple Fault Detection Programmable Logic Arrays"
	,journal=IEEETC
	,volume="C-29",year="1980",pages="518-522"}

@Article{AGAR81
	,key="Agarwal"
	,author="V.K. Agarwal and A.S.F. Fung"
	,title="Multiple Fault Testing of Large Circuits by Single
Fault Test Sets"
	,journal=IEEETC
	,volume="C-30",month="November",year="1981",pages="855-865"}

@InProceedings{AGRA84,
	Title="A Gate Level Model For {CMOS} Combinational Logic Circuits With Application To Fault Detection",
	Author="S.M. Reddy and V.D. Agrawal and  S.K. Jain",
	Organization="IEEE",
	BookTitle= PrDAC,
	Pages="504-509",
	Year="1984",
	key="Agrawal, V"}

@Inproceedings{PAGR84,
	Title="Test Generation At Switch Level",
	Author="Prathima Agrawal",
	Organization="IEEE",
	BookTitle= PrICCAD,
	Pages="128-130",
	Year="1984",
	key="Agrawal, P"}

@inproceedings{Aitk91
	,key="Aitken"
	,author="Robert C. Aitken"
	,title="Fault Location with Current Monitoring"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1991",pages="623-632"}

@inproceedings{Aitk92
	,key="Aitken"
	,author="Robert C. Aitken"
	,title="A Comparison of Defect Models for Fault Location with
Iddq Measurements"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1992",pages="778-787"}

@inproceedings{Aitk93
	,key="Aitken"
	,author="R.C. Aitken and P.C. Maxwell"
	,title="Design for Diagnosis with Iddq Measurements"
	,organization="The Materials Information Society"
	,booktitle= "Proceedings of the 19th International Symposium
for Testing and Failure Analysis"
	,year="1993",pages="151-154"}

@inproceedings{Aitk93itc
	,key="Aitken"
	,author="Robert C. Aitken"
	,title="A Comparison of Defect Models for Fault Location with Iddq Measurements"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1993",pages="1051-1060"}

@inproceedings{Aitk95
	,key="Aitken"
	,author="Robert C. Aitken"
	,title="Finding Defects with Fault Models"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1995",pages="498-505"}

@Book{AHO:ALGOR,
	Author="A.V. Aho and J.E. Hopcroft and J.D. Ullman",
	Key="Aho",
	Title="The Design and Analysis of Computer Algorithms",
	Publisher="Addison-Wesley Publishing Company",
	Year="1974"}

@Article{ALAR87
	,key="Al-Arian"
	,author="S.A. Al-Arian and D.P. Agrawal"
	,title="Physical Failures and Fault Models of {CMOS} Circuits"
	,journal=IEEETCS
	,volume="CAS-34",month="March",year="1987",pages="269-279"}

@article{ARMS72,
	Title="A deductive method for simulating faults in logic circuits",
	Author="D.B. Armstrong", 
	Journal=IEEETC,
	Year="1972",Month="May",
	Volume="C-21",Number="5",
	Pages="464-471",
	key="Armstrong"}

@InProceedings{Bala96,
        Author="H. Balachandran and D.M.H. Walker",
	Key="Balachandran",
        Title="Improvement of {SRAM}-Based Failure Analysis Using
Calibrated {Iddq} Testing",
	BookTitle= PrVTS,
	Pages="130-136",
        Year="1996"}

@InProceedings{BANE82,
	Author="P. Banerjee and J.A. Abraham",
	Key="Banerjee",
	Title="Fault Characterization of {VLSI} {MOS} Circuits",
	Organization="IEEE",
	BookTitle="Proc. of ICCC-82.",
	Pages="564-568",
	Year="1982",
	Annote="Gate to Source/Drain faults, PLA and Decoder fault models"}

@TechReport{Baze94,
	Author="Cyrus Bazeghi and Alvin Jee",
	Key="Baze", Address = "Computer Engineering Department",
	number ="UCSC-CRL-94-20",
	Title="Carafe User's Manual",
	Institution="University of California at Santa Cruz",Month="May",
	Year="1994"}	

@Article{BERN78
	,key="Bernard"
	,author="J. Bernard"
	,title="The IC Yield Problem:  A Tentative Analysis for {MOS/SOS} Circuits"
	,journal=IEEETED
	,volume="ED-25",year="1978",number="8",month="August",pages="939-944"}

@Article{Boll94,
	Author="S. Wayne Bollinger and Scott F. Midkiff",
	Key="Bollinger",
	Title="Test Generation for {IDDQ} Testing of Bridging Faults
in {CMOS} Circuits",
	Journal=IEEETCAD,
	Volume="13", Number="11",
	Pages="1413-1418", Month="November", Year="1994"}

@Article{BONE92
	,key="Boneh"
	,author="A. Boneh and J. Savir"
	,title="Statistical Resistance to Detection"
	,journal=IEEETC
	,volume="41",year="1992",number="1",month="January",pages="123-126"}

@article{BOWE85,
	Title="Low-Cost Testers:  Are they really low cost?",
	Author="Bowers, Jr., G.H. and B.G. Pratt",
	Journal=IEEEDTC,
	Year="1985", Month="June",
	Volume="2", Number="3",
	Pages="20-28",
	key="Bowers"}

@Article{Brah84,
	Author="D. Brahme and J. A. Abraham",
	Key="Brahme",
	Title="Functional Testing of Microprocessors",
	Journal=IEEETC,
	Volume="C-33",Number="6",Pages="475-485",Month="June",Year="1984"}

@Book{BREU,
	Author="M.A. Breuer and A.D. Friedman",
	Key="Breuer",
	Title="Diagnosis and Reliable Design of Digital Systems",
	Publisher="Computer Science Press",
	Year="1976"}

@InProceedings{Bruls91,
	Author="E.M.J.G. Bruels and F. Camerik and H.J. Kretschman and
J.A.G. Jess",
	Key="Bruls",
	Title="A generic method to develop a defect monitoring system
for {IC} processes",
	Organization="IEEE",
	BookTitle=PrITC,
	Pages="5218-227",
	Year="1991"}

@InProceedings{ISCAStest,
	Author="F. Brglez and H. Fujiwara",
	Key="Brglez",
	Title="A neutral netlist of 10 combinational benchmark circuits
	and a target translator in fortran",
	BookTitle="Proceedings of the IEEE International Symposium on
Circuits and Systems",
	Year="1985"}

@Article{BRYA83,
	Author="R.E. Bryant and M.D. Schuster",
	Key="Bryant",
	Title="Fault Simulation of {MOS} Digital Circuits",
	Journal="VLSI Design",
	Pages="24-30",
	Month="October",
	Year="1983",
	Annote="Mixed level fault simulator"}

@Manual{BRYA85,
	Author="R.E. Bryant and M.D. Schuster",
	Title="{FMOSSIM} - A Switch-Level Logic and Fault Simulator",
	Organization="Department of Computer Science, California Institute 
			of Technology",
	Month="August 22",
	Year="1985",
	Key="Bryant"}

@article{BRYA87,
	Title="Switch-Level Algorithms",
	Author="Randal E. Bryant",
	Journal=IEEEDTC,
	Year="1987", Month="August",
	Volume="4", Number="4",
	Pages="26-40",
	key="Bryant"}

@InProceedings{BRYA87dac,
	Author="R.E. Bryant and D. Beatty and K. Brace and K. Cho and
T. Sheffler",
	Key="Bryant",
	Title="{COSMOS}: A Compiled Simulator for {MOS} Circuits",
	Organization="ACM and IEEE",
	Pages="9-16", Year="1987",
	BookTitle= PrDAC}

@InProceedings{CASE76,
	Author="G.R. Case",
	Key="Case",
	Title="Analysis of Actual Fault Mechanisms in {CMOS} Logic Gates",
	Organization="ACM and IEEE",
	Pages="265-269",
	Year="1976",
	BookTitle= PrDAC,
	Annote="Models sequential behavior as combinational with an assigned probability"}
-
@Article{Chak90,
	Author="S. Chakravarty and H.B. Hunt",
	Key="Chakravarty",
	Title="On Computing Signal Probability and Detection
Probability of Stuck-at Faults",
	journal=IEEETC,
	Month="November",Year="1990",Volume="C-39",Number="11",
	Pages="1369-1377"}

@InProceedings{Chak93dac,
	Author="S. Chakravarty and Y. Gong",
	Key="Chakravarty",
	Title="An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits",
	Organization="ACM and IEEE",
	Pages="520-524",
	Year="1993",
	BookTitle= PrDAC}

@InProceedings{Chak92Jetta,
	Author="S. Chakravarty and M. Liu",
	Key="Chakravarty",
	Title="Algorithms for {IDDQ} Measurement Based Diagnosis of Bridging Faults",
	Month="December",Year="1992",Volume="3",Number="4",
	Pages="377-386",
	Journal= JETTA}

@Article{Cham94,
	Author="V.H. Champac and A. Rubio and J. Figueras",
	Key="Champac",
	Title="Electrical Model of the Floating Gate Defect in {CMOS ICs}:
Implications on {Iddq} Testing",
	journal=IEEETCAD,
	Month="March",Year="1994",Volume="13",Number="3",
	Pages="359-369"}

@InProceedings{CHANG96,
	Author="Jonathan Chang and Edward McCluskey",
	Key="Chang",
	Title="Quantitative Analysis of Very-Low-Voltage Testing",
	Organization="IEEE",
	Pages="332-343",
	Year="1996",
	BookTitle= PrVTS}

@InProceedings{CHAN83,
	Author="R. Chandramouli",
	Key="Chandramouli",
	Title="On Testing Stuck-Open Faults",
	Organization="IEEE",
	Pages="258-265",
	Year="1983",
	BookTitle= PrFTCS}

@Article{CHAP74,
	Author="S.G. Chappell and C.H. Elmendorf and L.D. Schmidt",
	Key="Chappell",
	Title="{LAMP}:  Logic Circuit Simulation",
	journal="Bell System Technical Journal",
	Month="October",Year="1974",Volume="53",pages="1451-1476"}

@InProceedings{CHAT87,
	Author="A. Chatterjee and J. Abraham",
	Key="Chatterjee",
	Title="Test Generation for Arithmetic Units by Graph Labelling",
	Organization="IEEE",
	Pages="284-289",
	Year="1987",
	BookTitle= PrFTCS}

@Article{Chat90,
	Author="A. Chatterjee and J.A. Abraham",
	Key="Chatterjee",
	Title="The Testability of Generalized Counters Under Multiple
Fault Cells",
	journal=IEEETC,
	Month="November",Year="1990",Volume="C-39",Number="11",
	Pages="1378-1385"}

@Inproceedings{CHEN84,
	Title="Test Generation For {MOS} Circuits",
	Author="Harry H. Chen and Robert G. Mathews and John A. Newkirk",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="70-79",
	Year="1984",
	key="Chen"}

@PhDThesis{ChengPHD,
	Author="Wu-Tung Cheng",
	Title="Testing and Error Detection in Interative Logic Arrays",
	School="University of Illinois at Urbana-Champaign, College of Engineering",
	Month="August", number="UILU-ENG-85-2234",
	Year="1985", Key="Cheng"}

@Article{Cheng87J,
	Author="W-T. Cheng and J.H. Patel",
	Key="Cheng",
	Title="Testing in Two-Dimensional Iterative Logic Arrays",
	journal="Comput. Math. Applic.",
	Year="1987",Volume="13",Number="5/6",
	Pages="443-454"}

@Article{Cheng90,
	Author="W. Cheng and J.H. Patel",
	Key="Cheng",
	Title="A Minimum Test Set for Multiple Fault Detection in
Ripple Carry Adders",
	journal=IEEETC,
	Month="July",Year="1987",Volume="C-36",Number="7",
	Pages="891-895"}

@Inproceedings{Lavo97,
        Title="Bridging Fault Diagnosis in the Absence of Physical Information",
        Author="David Lavo and Brian Chess and Tracy Larrabee and
F. Joel Ferguson and Jayashree Saxena and Kenneth Butler",
        Organization="IEEE",
	Booktitle="Proceedings of the 1997 International Test Conference",
        Pages="887-893", 
        Year="1997"}


@Inproceedings{Chess95iccad,
        Title="Diagnosing Realistic Bridging Faults with Stuck-at Dictionaries",
        Author="Brian Chess and David Lavo and  F. Joel Ferguson and Tracy Larrabee",
        Booktitle="Proceedings of International Conference on Computer-Aided Design",
        Pages="185-192",
        Year="1995"}

@Inproceedings{Chess94,
        Title="Testing {CMOS} Logic Gates for Realistic Shorts",
        Author="Brian Chess and Anthony Freitas and  F. Joel Ferguson and Tracy Larrabee",
        Booktitle=PrITC,
        Pages="395-402",
        Year="1994"}

@Inproceedings{Chess93,
        Title="Bridge Fault Simulation Strategies for CMOS Integrated Circuits",
        Author="Brian Chess and Tracy Larrabee",
        Booktitle=PrDAC,
        Pages="458-462",
        Year="1993"}
					
@Inproceedings{CHIA82
	,key="Chiang"
	,author="K. Chiang and Z.G. Vranesic"
	,title="Test Generation for {MOS} Complex Gate Networks"
	,organization="IEEE"
	,BookTitle= PrFTCS
	,year="1982",pages="149-157"}

@Inproceedings{CHIA83
	,key="Chiang"
	,author="K. Chiang and Z.G. Vranesic"
	,title="On Fault Detection in {CMOS} Logic Networks"
	,organization="ACM and IEEE"
	,BookTitle= PrDAC
	,year="1983",pages="50-56"}

@Article{CHIA84,
	Author="K. Chiang and Z.G. Vranesic",
	Key="Chiang",
	Title={Comments on "Fault Diagnosis of {MOS} Combinational Networks"},
	journal=IEEETC,
	Month="October",Year="1984",Volume="c-33",Number="10",pages="947"}

@Article{CHo88,
	Author="Umakanta Choudhury and Alberto Sangiovanni-Vincentelli",
	Key="Choudhury",
	Title="Constraint-Based Channel Routing for Analog and Mixed
Analog/Digital Circuits",
	journal=IEEETCAD,
	Month="April",Year="1993",Volume="12",Number="4",pages="497-510"}

@Article{CLIF80
	,key="Cliff"
	,author="R.A. Cliff"
	,title="Acceptable Testing of {VLSI} Components Which Contain Error Correctors"
	,journal=IEEETC
	,volume="C-29",year="1980",number="2"
	,month="February",pages="125-134"}

@Article{COX88,
	Author="Henry Cox and Janusz Rajski",
	Key="Cox",
	Title="A Method of Fault Analysis for Test Generation and
Fault Diagnosis",
	journal=IEEETCAD,
	Month="July",Year="1988",Volume="7",Number="7",pages="813-833"}

@Article{COX94,
	Author="Henry Cox and Janusz Rajski",
	Key="Cox",
	Title="On Necessary and Nonconflicting Assignments in
Algorithmic Test Pattern Generation",
	journal=IEEETCAD,
	Month="April",Year="1994",Volume="13",Number="4",pages="515-530"}

@Inproceedings{CRAP87,
	Title="Testing {CMOS} Idd on Large Devices",
	Author="C. Crapuchettes",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="310-315", Year="1987",
	key="Crapuchettes"}

@Article{DAEH81
	,key="Daehn"
	,author="W. Daehn and J. Mucha"
	,title="A Hardware Approach to Self-Testing of Large Programmable Logic Arrays"
	,journal=IEEETC
	,volume="C-30",year="1981",pages="829-833"}

@Article{Damp87,
	Author="R.I. Damper and N. Burgess",
	Key="Damper",
	Title="{MOS} Test Pattern Generation Using Path Algebras",
	Journal=IEEETC,
	Volume="C-36", Number="9", Pages="1123-1128",
	Month="September", Year="1987"}
	% Switch-level test generation using algebra.

@Inproceedings{Das90,
	Title="An Experimental Study on Reject Ratio Prediction for
{VLSI} Circuits:  Kodomo Revisited",
	Author="D. Das and S. Seth and P. Wagner and J. Anderson and
V.D. Agrawal ",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="712-720", Year="1990",
	key="Das"}

@TechReport{DEKK87,
	Author=" Rob Dekker",
	Key="Dekker",
	Title="Fault Modeling and Self-Test of Static Random Access Memories",
	Institution="Philips Research Laboratories Eindhoven",Month="August",Year="1987"}
%  *

@TechReport{DekkM,
	Author="Rob Dekker",
	Key="Dekker", Address = "Department of Electrical Engineering",
	Number ="1-68340-28",
	Title="Fault Modeling and Self-test of Static Random Access Memories",
	Institution="Delf University of Technology, The Netherlands",Year="1987"}

@Inproceedings{Dekk88a,
	Title="Fault Modeling and Test Algorithm Development for
Static Random Access Memories",
	Author="R. Dekker and F. Beenker and L. Thijssen",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="343-352", Year="1988",
	key="Dekker"}

@Inproceedings{Dekk88b,
     Title="A Realistic Self-Test Machine for Static Random Access Memories",
	Author="R. Dekker and F. Beenker and L. Thijssen",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="353-361", Year="1988",
	key="Dekker"}

@article{Dekk89,
	Title="Realistic Built-in Self-Test for Static {RAMS}",
	Author="R. Dekker and F. Beenker and L. Thijssen",
	Journal=IEEEDTC,
	Year="1989", Month="February",
	Volume="6", Number="1",
	Pages="26-34",
	key="Dekker"}

@Article{Deva92,
	Author="S. Devadas",
	Key="Devadas",
	Title="Synthesis of Robust Delay-Fault-Testable Circuits: Theory",
	Journal=IEEETCAD,
	Volume="11", Number="1", Pages="87-101",
	Month="January", Year="1992"}

@Article{DIAS75,
	Author="F.J.O. Dias",
	Key="Dias",
	Title="Fault Masking in Combinational Logic Circuits",
	Journal=IEEETC,
	Volume="C-24", Number="5", Pages="476-482",
	Month="May", Year="1975"}
	
@Article{DIAS76,
	Author="F.J.O. Dias",
	Key="Dias",
	Title="Truth-Table Verification of an Iterative Logic Array",
	Journal=IEEETC,
	Volume="C-25", Number="6", Pages="605-613",
	Month="June", Year="1976",
	Annote="WRONG"}	

@article{Ditz87,
	Title="Using {CAD} Tools in the Deign of {CRISP}",
	Author="D.R. Ditzel and A.D. Berenbaum",
	Journal=IEEEDTC,
	Year="1987", Month="June",
	Volume="4", Number="3",
	Pages="21-31",
	key="Ditzel"}

@inproceedings{Eichelberger,
AUTHOR = "Eichelberger, E. and Williams, T.",
TITLE = "A logic design structure for {LSI} testability",
BOOKTITLE = "Proceedings of the 14th Design Automation Conference",
YEAR = 1977,
ORGANIZATION = "IEEE"
}
     
@inproceedings{Elo90
	,key="Elo"
	,author="R.B. Elo"
	,title="An Empirical Relationship Between Test Transparancy
and Fault Coverage"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1990",pages=""}

@InProceedings{ELZI81,
	Author="Y.M. El-ziq and R. Cloutier",
	Key="El-ziq",
	Title="Functional-level test generation for stuck-open in {CMOS} {VLSI}",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="536-546",
	Year="1981"}

@Article{ELZI82,
	Author="Y.M. El-ziq and S.Y.H. Su",
	Key="El-ziq",
	Title="Fault Diagnosis of {MOS} Combinational Networks",
	journal=IEEETC,
	Month="February",Year="1982",Volume="C-31",Number="2",pages="129-139",
	Annote="Test set for multiple transistors stuck on/off"}

@Article{ELZI83,
	Author="Y.M. El-ziq",
	Key="El-ziq",
	Title="Classifying, Testing, and Eliminating {VLSI} {MOS} Failures",
	Journal="VLSI Design",Pages="30-33",Month="September",Year="1983",
	Annote="Describes easy and difficult faults to test.  Some design for testability"}

@Article{Fava91J,
	key="Favalli",
	author="M. Favalli and P.Olivo and F. Somenzi and B. Ricco",
	Title="Fault Simulation for General {FCMOS} {IC}s",
	Journal=JETTA,
	Month="June",Year="1991",volume="2",number="2",pages="181-190"}

@Article{Fava91,
	key="Favalli",
	author="M. Favalli and P.Olivo and M. Damiani and B. Ricc\'{o}",
	Title="Fault Simulation of Unconventional Faults in {CMOS} Circuits",
	Journal=IEEETCAD,
	Month="May",Year="1991",volume="CAD-10",number="5",pages="677-682"}

@Article{Fava92,
	key="Favalli",
	author="M. Favalli and P.Olivo and B. Ricc\'{o}",
	Title="A Probabilistic Fault Model for Analog Faults in Digital {CMOS} Circuits",
	Journal=IEEETCAD,
	Month="November",Year="1992",volume="CAD-11",number="11",
	pages="1459-1462"}

@Article{Fava96,
	key="Favalli",
	author="M. Favalli and M. Dalpasso and P. olivo",
	Title="Modeling and Simulation of Broken Connections in {CMOS} {IC}s",
	Journal=IEEETCAD,
	Month="July",Year="1996",volume="15",number="7",pages="808-814"}

@Article{Felt91
	,key="Feltham"
	,author="Derek Feltham and Wojciech Maly"
	,title="Physically Realistic Fault Models for Analog {CMOS} Neural Networks"
	,journal="IEEE Journal of Solid-State Circuits"
      ,volume="26",year="1991",number="9",month="September",pages="1223-1229"}
	
@Inproceedings{Ferg83,
	Title="The Design of Two Easily-Testable {VLSI} Array Multipliers",
	Author="F. J. Ferguson and J. P. Shen",
	Organization="IEEE",
	Booktitle= "6th Symposium on Computer Arithmetic",
	Pages="2-9", Year="1983",
	key="Ferguson"}

@TechReport{Ferg83t,
	Author=" F. Joel Ferguson and John P. Shen",
	Key="Ferguson", Address = CMUSRC, number ="CMU-83-8",
	Title="The Design of Easily-Testable {VLSI} Array Multipliers",
	Institution="Carnegie Mellon University",Month="February",Year="1983"}
	
@Inproceedings{Ferg85,
	Author="F. Joel Ferguson and John P. Shen",
	Key="Ferguson",
	Title="Multiple-Fault Test Sets for {MOS} Complex Gates",
	Organization="IEEE",
	BookTitle= PrICCAD,
	Pages="36-38", Year=1985}
	
@TechReport{Ferg86t,
	Author=" F. Joel Ferguson and John P. Shen",
	Key="Ferguson", Address = CMUSRC, number ="CMU-86-10",
	Title="Multiple-Fault Test Sets for {MOS} Complex Gates",
	Institution="Carnegie Mellon University",Month="April",Year="1986"}

@PhDThesis{FergPHD,
	Author="F. Joel Ferguson",
	Title="Inductive Fault Analysis of {VLSI} Circuits",
	School="Carnegie Mellon University, Department of Electrical and Computer Engineering",
	Month="October", number="CMUCAD-87-51",
	Year="1987", Key="Ferguson"}

@TechReport{Ferg87,
	Author=" F. Joel Ferguson",
	Key="Ferguson", Address=CMUSRC, number ="CMUCAD-87-51",
	Title="Inductive Fault Analysis of {VLSI} Circuits",
	Institution="Carnegie Mellon University",Month="December",Year="1987"}

@Article{Ferg88,
	Author="F. Joel Ferguson and John P. Shen",
	Key="Ferguson",
	Title="A {CMOS} Fault Extractor for Inductive Fault Analysis",
	journal=IEEETCAD,
	Month="November",Year="1988",Volume="7",Number="11",pages="1181-1194"}

@Inproceedings{Ferg88itc,
	Title="Extraction and Simulation of Realistic {CMOS} Faults
	       with Inductive Fault Analysis ",
	Author="F. Joel Ferguson and John P. Shen",
	Organization="IEEE",
	Booktitle=PrITC,
	Pages="475-484", Year="1988",
	key="Ferguson"}

@TechReport{Ferg88t,
	Author="F. Joel Ferguson",
	Key="Ferguson", Address = "Computer Engineering Department",
	number ="UCSC-CRL-88-22",
	Title="Detection of Multiple Faults in {MOS} Circuits",
	Institution="University of California at Santa Cruz",Month="February",
	Year="1989"}

@Article{Ferg90TCAD,
	Author="F. Joel Ferguson",
	Key="Ferguson",
	Title="Detection of Multiple Faults in {MOS} Circuits",
	journal="IEEE Transactions on Computer-Aided Design",
	Month="September",Year="1990",Volume="9",Number="9",pages="1009-1014"}

@Inproceedings{Ferg90itc,
	Title="Testing for Parametric Faults in Static {CMOS} Circuits",
	Author="F. Joel Ferguson and Martin Taylor and Tracy Larrabee",
	Organization="IEEE",
	Booktitle=PrITC,
	Pages="436-443", Year="1990",
	key="Ferguson"}

@Inproceedings{Ferg91test,
	Title="Test Pattern Generation for Current Testable Faults in Static {CMOS} Circuits",
	Author="F. Joel Ferguson and  Tracy Larrabee",
	Organization="IEEE",
	Booktitle="Proceedings of the 1991 VLSI Test Symposium",
	Pages="297-302", Year="1991",
	key="Ferguson"}

@Inproceedings{Ferg91itc,
	Title="Test Pattern Generation for Realistic Bridge Faults in {CMOS} {IC}s",
	Author="F. Joel Ferguson and Tracy Larrabee",
	Organization="IEEE",
	Booktitle=PrITC,
	Pages="492-499", Year="1991",
	key="Ferguson"}

@Inproceedings{Ferg93,
	Title="Physical Design for Testability for Bridges in {CMOS} Circuits",
	Author="F. Joel Ferguson",
	Organization="IEEE",
	Booktitle="Proceedings of the 1993 VLSI Test Symposium",
	Pages="290-295", Year="1993",
	key="Ferguson"}

@Article{FRID74,
	Author="Marek Fridrich and Wayne A. Davis",
	Key="Fridrich",
	Title="Minimal Fault Tests for Combinational Networks",
	Journal=IEEETC,Volume="C-23",Number="8",
	Pages="850-859",Month="August",Year="1974"}

@Article{FRIE73,
	Author="A.D. Friedman",
	Key="Friedman",
	Title="Easily Testable Iterative Systems",
	Journal=IEEETC,Volume="C-22",Number="12",
	Pages="1061-1064",Month="December",Year="1973"}

@Article{FUJI81
	,key="Fujiwara"
	,author="H. Fujiwara and K. Kinoshita"
	,title="A Design of Programmable Logic Arrays with Universal Tests"
	,journal=IEEETC
	,volume="C-30",year="1981",pages="823-828"}

@Article{FUJI83
	,key="Fujiwara"
	,author="H. Fujiwara and T. Shimono"
	,title="On the Acceleration of Test-Generation Algorithms"
	,journal=IEEETC
	,volume="C-32",year="1983",number="12",month="December",pages="1137-1144"}

@Article{GALI80
	,key="Galiay"
	,author="J. Galiay and Y. Crouzet and M. Vergniault"
	,title="Physical Versus Logical Fault Models in {MOS} {LSI} Circuits: Impact on Their Testability"
	,journal=IEEETC
	,volume="C-29",year="1980",number="6",month="June",pages="527-531"}

@Article{GAUL72,
	Author="J.W. Gault and J.P. Robinson and S.M. Reddy",
	Key="Gault",
	Title="Multiple Fault Detection in Combinational Networks",
	Journal=IEEETC,
	Volume="C-21", Number="1", Pages="31-36",Month="January",Year="1972"}
% At least 4 faults for UFS; Creates T0,T1 for ff gate; Spanning and
% Sensitizing faults; For Maximal test sets non-fanned out control input for
% each primary gate-detects all faults; all faults detected in
% two-level circuits with any SSA test.

@InProceedings{Gayle93,
	Author="Rick Gayle",
	Key="Gayle",
	Title="The cost of Quality:  Reducing {ASIC} Defects with IDDQ, At-Speed Testing, and Increased Fault Coverage",
	BookTitle= PrITC,
	Pages="285-292",
	Year="1993"}

@InProceedings{Ghos89,
	Author="A. Ghosh and S. Devadas and A.R. Newton",
	Key="Ghosh",
	Title="Test Generation for Highly Sequential Circuits",
	BookTitle= PrICCAD,
	Pages="362-365",
	Year="1989"}

@Article{Ghos91
	,key="Ghosh"
	,author="A. Ghosh and S. Devadas and A.R. Newton"
	,title="Test Generation and Verification for Highly Sequencial Circuits"
	,journal=IEEETCAD
	,volume="CAD-10",year="1991",number="15",month="March",pages="652-667"}

@Article{Gira95,
	key="Girard",
	author="P. Girard and C. Landrault and S. Pravossoudovitch",
	Title="An Advanced Diagnostic Method for Delay Faults in
         Combinational Faulty Circuits",
	Journal=JETTA,
	Month="June",Year="1995",volume="6",number="3",pages="277-294"}

@Inproceedings{GOEL80
	,key="Goel"
	,author="P. Goel"
	,title="Test generation costs analysis and projections"
	,organization="IEEE"
	,BookTitle= PrDAC
	,year="1980"}

@Article{GOEL81,
	Key="Goelb",
	Author="P. Goel",
	Title="An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits",
	Journal=IEEETC,
	Volume="C-30", Pages="215-222",
	Month="March", Year="1981"}

@Article{GOLD79,
	Author="L.H. Goldstein",
	Title="Controllability/Oberservability Analysis of Digital Circuits",
	Journal=IEEETCS,
	Volume="CAS-26", Pages="685-693",
	Month="Sept.", Year="1979", Key="Goldstein"}

@Article{GRAY78,
	Author="F.G. Gray and R.A. Thompson",
	Key="Gray",
	Title="Fault Detection in Bilateral Arrays of Combinational Cells",
	Journal=IEEETC,
	Volume="C-27", Number="12", Pages="1206-1213",Month="December",	Year="1978"}
@Inproceedings{Gree92,
        Author="G. Greenstein and J. Patel",
        Organization="IEEE",
        Title="{EPROOFS}: a {CMOS} bridging fault simulator",
        Booktitle = PrICCAD,
        Year="1992",
        Pages="268--271"}
						
@InProceedings{GUPT83,
	Author="A. Gupta",
	Key="Gupta",
	Title="{ACE}:  A Circuit Extractor",
	Organization="ACM IEEE",
	Year="1983",
	BookTitle= PrDAC,
	Annote="Models sequential behavior as combinational with an assigned probability"}

@Article{Gupt88,
	Key="gupta",
	Author="G. Gupta and N.K. Jha",
	Title="A Universal Test Set for {CMOS} Circuits",
	Journal=IEEETCAD,
	Volume="7", Number="8", Pages="590-597",
	Month="May", Year="1988"}

@Article{Gyvez92,
        Author="J. Pineda de Gyvez and C. Di",
        Title="{IC} Defect Sensitivity for Footprint-Type Spot Defects",
        Journal=IEEETCAD, Month="May", pages="638-658",
        Year="1992"}

@InProceedings{Hao91,
	Author="Hong Hao and Edward McCluskey",
	Key="Hao",
	Title="Resistive Shorts within {CMOS} Gates",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="292-301",
	Year="1991"}

@Article{Hao93,
	Author="Hong Hao and Eduward J. McCluskey",
	Key="Hao",
	Title="Analysis of Gate Oxide Shorts in {CMOS} Circuits",
	Journal=IEEETC,
	Month="December",Year="1993",Volume="42",Number="12",pages="1510-1517"}

@InProceedings{Hao93itc,
	Author="Hong Hao and Edward McCluskey",
	Key="Hao",
	Title="Very-low-voltage Testing for Weak {CMOS} Logic {ICs}",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="275-284",
	Year="1993"}

@InProceedings{HASS83,
	Author="S.Z. Hassan and E.J. McCluskey",
	Key="Hassan",
	Title="Testing {PLAs} Using Multiple Parallel Signature Analyzers",
	Organization="IEEE",
	BookTitle= PrFTCS,
	Pages="422-425",
	Year="1983"}

@InProceedings{Hawk86,
	Author="C.F. Hawkins and J.M. Soden",
	Key="Hawkins",
	Title="Reliability and Electrical Properties of Gate Oxide
Shorts in {CMOS} {IC}s",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="443-451",
	Year="1986"}

@article(Hawk89,
	author="Charles F Hawkins and Jerry M Soden 
		and Ron R Fritzemeier and Luther K Horning",
	title="Quiescent Power Supply Current Measurement
		for {CMOS} {IC} Defect Detection",
	journal="{IEEE} Transactions On Industrial Electronics",
	year=1989,
	month="May")

@InProceedings{Hawk94,
	Author="Chuck Hawkins and Jerry Soden and Alan Righter and F. Joel Ferguson",
	Key="Hawkins",
	Title="Defect Models - An Overdue Paradigm for {CMOS} {IC} testing",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="413-425",
	Year="1994"}

@article{HAYE85,
	Title="Fault Modeling",
	Author="John P. Hayes",
	Journal=IEEEDTC,
	Year="1985", Month="April",
	Volume="2", Number="2",
	Pages="88-95",
	key="Hayes"}

@Book{Hein88
	,key="Heinbuch"
	,author="Dennis V. Heinbuch"
	,title="{CMOS3} Cell Library"
	,publisher="Addison-Wesley Publishing Company"
	,year="1988"}

@InProceedings{Hend91,
	Author="C.L. Henderson and J.M. Soden and C.F. Hawkins",
	Key="Henderson",
	Title="The Behavior and Testing Implications of {CMOS IC}
Logic Gate Open Circuits",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="302-310",
	Year="1991"}

@Book{Hodges83
	,key="Hodges"
	,author="David Hodges and Horace Jackson"
	,title="Analysis and Design of Digital Integrated Circuits"
	,publisher="McGraw-Hill Book Company"
	,year="1983"}

@TechReport{HON,
	Author="R.W. Hon and C.H. Sequin",
	Key="Hon",
	Title="A Guide to {LSI} Implementation",
	Institution="Xerox",
	Number="SSl-79-7",
	Month="January",
	Year="1980"}

@InProceedings{Hong88,
	Author="S.J. Hong",
	Key="Hong",
	Title="An Easily Testable Parallel Multiplier?????",
	Organization="IEEE",
	Pages="214-219",
	Year="1988",
	BookTitle= PrFTCS}

@Article{Hong90,
	Author="Sung Je Hong",
	Key="Hong",
	Title="The Design of a Testable Parallel Multiplier",
	Journal=IEEETC,
	Month="March",Year="1990",Volume="39",Number="3",pages="411-416"}

@InProceedings{Horn87,
	Author="L.K. Horning and J.M. Soden and R.R. Fritzemeier and
C.F. Hawkins",
	Key="Horning",
	Title="Measurements of Quiescent Power Supply Current for
{CMOS ICs} in Production Testing",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="300-309",
	Year="1987"}

@article{Hwan88,
	Title="On an Improved Design Approach for {C-testable}
Orthogonal Iterative Arrays",
	Author="C.G. Hwang and R.W. Dutton",
	Journal=IEEETCAD,
	Year="1988", Month="May",
	Volume="7", Number="5",
	Pages="578-583",
	key="Hwang"}

@article{Huff54a,
	Title="The Synthesis of Sequential Switching Circuits",
	Author="D.A. Huffman",
	Journal="J. Franklin Institute",
	Year="1954", Month="March",
	Volume="257", Number="3",
	Pages="161-191",
	key="Huffman"}

@article{Huff54b,
	Title="The Synthesis of Sequential Switching Circuits",
	Author="D.A. Huffman",
	Journal="J. Franklin Institute",
	Year="1954", Month="April",
	Volume="257", Number="4",
	Pages="275-303",
	key="Huffman"}

@article{HUGH88,
	Title="Multiple Fault Detection using Single Fault Test Sets",
	Author="J.L.A. Hughes",
	Journal=IEEETCAD,
	Year="1988", Month="January",
	Volume="7", Number="1",
	Pages="100-108",
	key="Hughes"}

@Article{Huis88,
	Author="Leendert M. Huisman",
	Key="Huisman",
	Title="The Reliability of Approximate Testability Measures",
	Journal=IEEEDTC,
	Month="December",Year="1988",Volume="5",Number="6",pages="57-67"}

@Article{IPRI79
	,key="Ipri"
	,author="A.C. Ipri"
	,title="Impact of Design Rule Reduction on Size, Yield, and Cost of Integrated Circuits"
	,journal="Solid State Technology"
	,year="1979",month="February",pages="85-89"}

@InProceedings{Iyen88a,
	Author="V.S. Iyengar and B.K. Rosen and I. Spillinger",
	Key="Iyengar",
	Title="Delay Test Generation 1 -- Concepts and Coverage Metrics",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="857-866",
	Year="1988"}

@InProceedings{Iyen88b,
	Author="V.S. Iyengar and B.K. Rosen and I. Spillinger",
	Key="Iyengar",
	Title="Delay Test Generation 2 -- Algebra and Algorithms",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="867-876",
	Year="1988"}

@Inproceedings{Jaco89,
	Title="{FANTESTIC}: Towards a Powerful Fault Analysis and Test
Pattern Generator for Integrated Circuits ",
	Author="M. Jacomet",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="633-642", Year="1989",
	key="Jacomet"}

@Article{JAIN85,
	Author="S.K. Jain and V.D. Agrawal",
	Key="Jain",
	Title="Modeling and Test Generation Algorithms for {MOS} Circuits",
	Journal=IEEETC,
	Month="May",Year="1985",Volume="c34",Number="5",pages="426-433"}

@Article{JAIN85b,
	Author="S.K. Jain and V.D. Agrawal",
	Key="Jain",
	Title="Statistical Fault Analysis",
	Journal=IEEEDTC,
	Month="February",Year="1985",Volume="2",Number="1",pages="38-44"}

@Article{JAST82
	,key="Jastrzebski"
	,author="L. Jastrzebski"
	,title="Origin and Control of Material Defects in Silicon {VLSI} Technologies:  An Overview"
	,journal="IEEE Journal of Solid-State Circuits"
	,volume="SC-17",year="1982",number="2",month="April",pages="105-117"}
	
@TechReport{Jee90man,
	Author="Alvin Jee",
	Key="Jee", Address = "Computer Engineering Department",
	number ="UCSC-CRL-90-61",
	Title="Carafe User's Manual",
	Institution="University of California at Santa Cruz",Month="February",
	Year="1991"}	

@TechReport{Jee91,
	Author="Alvin Jee",
	Key="Jee", Address = "Computer Engineering Department",
	number ="UCSC-CRL-91-24",
	Title="Carafe: An Inductive Fault Analysis Tool for {CMOS} {VLSI} Circuits",
	Institution="University of California at Santa Cruz",Month="February",
	Year="1991"}	


@InProceedings{Jee93,
        Author="Alvin Jee and F. Joel Ferguson",
	Key="Jee",
        Title="Carafe:  An Inductive Fault Analysis Tool for {CMOS} {VLSI} Circuits",
	BookTitle= "Proceedings of the IEEE VLSI Test Symposium",
	Pages="92-98",
        Year="1993"}

@InProceedings{Jee93istfa,
        Author="Alvin Jee and F. Joel Ferguson",
	Key="Jee",
        Title="Carafe:  A Software Tool for Failure Analysis",
	BookTitle= "Proceedings of International Symposium for Testing and Fault Analysis",
	Pages="143-149",
        Year="1993"}

@InProceedings{Jee97,
        Author="Alvin Jee and F. Joel Ferguson",
	Key="Jee",
        Title="A Methodology for Characterizing Cell Testability",
	BookTitle= PrVTS,
	Pages="384-390",
        Year="1997"}

@PhDThesis{Jee96dis,
	Author="Alvin Jee",
	Title="Measuring Cell Testability",
	School="University of California, Santa Cruz, Department of Computer Engineering",
	Month="July", Year="1996", number="??????"}

@InProceedings{Jee94,
        Author="Alvin Jee and F. Joel Ferguson",
	Key="Jee",
        Title="An Analysis of Shorts in {CMOS} Standard Cell Circuits",
	BookTitle= PrASIC,
	Pages="362-365",
        Year="1994"}

@InProceedings{JHA84,
	Author="N.K. Jha and J.A. Abraham",
	Key="Jha",
	Title="Testable {CMOS} Logic Circuits under Dynamic Behavior",
	Organization="IEEE",
	BookTitle= PrICCAD,
	Pages="131-133",
	Year="1984"}
	@Comment{Previously in the key ABRA84}

@Inproceedings{JHA85,
	Title="Detecting Multiple Faults in {CMOS} Circuits ",
	Author="N.K. Jha",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="514-519", Year="1985",
	key="Jha"}
% Stuck OPEN Only if one of the transistors is not a member of a loop.

@Article{JHA88CAD,
	Author="N.K. Jha",
	Key="Jha",
	Title="Testing of Multiple Faults in Domino-{CMOS}",
	Journal=IEEETCAD,
	Month="January",Year="1988",Volume="7",Number="1",pages="109-116"}

@Article{JHA88,
	Author="N.K. Jha",
	Key="Jha",
	Title="Multiple Stuck-Open Fault Detection in {CMOS} Logic Circuits",
	Journal=IEEETC,
	Month="April",Year="1988",Volume="37",Number="4",pages="426-432"}

@Inproceedings{John91,
        Title="Automatic Synthesis of Self-Test using ASyST",
        Author="Peter Johnson and F. Joel Ferguson",
        Organization="IEEE",
	Booktitle="Proceedings of the 1991 VLSI Test Symposium",
        Pages="67-72", 
        Year="1991"}

@InProceedings{KAUT67,
	Author="W.H. Kautz",
	Key="Kautz",
	Title="Testing for Faults in Combinational Cellular Logic Arrays",
	Organization="ACM",
	BookTitle="Proc. 8th Annu. Symp. Switching and Automata Theory",
	Pages="161-173",
	Year="1967"}

@InProceedings{KAPU91,
	Author="R. Kapur and K. Butler and D Ross and M.R. Mercer",
	Key="Kapur",
	Title="On Bridging Fault controllability and observability and
their correlations to detectability",
	BookTitle="Proc. 2nd Annu. European. Test Conf.",
	Pages="333-330",
	Year="1991"}

@Inproceedings{Kapu92,
	Title="All Tests for a Fault are Not Equally Valuable for
Defect Detection",
	Author="R. Kapur and J. Park and M.R. Mercer",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="762-769", Year="1992",
	key="Kapur"}

@Inproceedings{KEAT87,
	Title="A New Approach to Dynamic Idd Testing",
	Author="M. Keating",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="316-321", Year="1987",
	key="Keating"}

@Inproceedings{Khare95,
	Title="Inductive Contamination Analysis ({ICA}) with {SRAM} Applications",
	Author="J. Khare and W. Maly",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="552-560", Year="1995",
	key="Khare"}

@Article{Khare95TSM
	,key="Khare"
	,author="J. Khare and W. Maly and S. Griep and D. Schmitt-Landsiedel"
	,title="Yield-oriented computer-aided defect diagnosis"
	,journal=IEEETSM
	,volume="8",month="May",year="1995",pages="195-206"}


@Article{KIM88,
	key="Kim",
	author="Kwanghyun Kim and Dong Ha and Joseph Tront",
	Title="On Using Signature Registers as Pseudorandom Pattern Generatore in Built-in Self-Testing",
	Journal=IEEETCAD,
	Month="August",Year="1988",volume="7",number="8",pages="919-928"}

@Article{KOEH83,
	Author="B. Koehler",
	Key="Koehler",
	Title="Designing a Microcontroller 'Supercell' for Testability",
	Journal="VLSI Design",
	Pages="44-46",
	Month="October",
	Year="1983"}

@inproceedings{KOEP87
	,key="Koeppe"
	,author="Siegmar Koeppe"
	,title="Optimal Layout to Avoid {CMOS} Stuck-Open Faults"
	,organization="IEEE"
	,booktitle= PrDAC
	,year="1987",pages="829-835"}

@Article{KOHA72,
	Author="I. Kohavi and Z. Kohavi",
	Key="Kohavi",
	Title="Detection of multiple faults in combinational logic networks",
	Journal=IEEETC,
	Volume="C-21", Number="6",
	Pages="556-568", Month="June", Year="1972"}
% All faults in two-level circuits detected by SSA test set

@PhDThesis{Konukthesis,
	Author="Haluk Konuk",
	Title="Testing for Opens in Digital {CMOS} Circuits",
	School="University of California at Santa Cruz, Department of Computer Engineering",
	Month="February", number="96-34",
	Year="1996", Key="Konuk"}

@Inproceedings{Konu97,
        Title="Oscillation and Sequential Behavior Caused by
Interconnect Opens in Digital {CMOS} Circuits",
        Author="Haluk Konuk and F. Joel Ferguson",
        Organization="IEEE",
	Booktitle="Proceedings of the 1997 International Test Conference",
        Pages="597-606", 
        Year="1997"}

@Inproceedings{Konu96,
        Title="An Unexpected Factor in Testing for CMOS Opens: The die surface",
        Author="Haluk Konuk and F. Joel Ferguson",
        Organization="IEEE",
	Booktitle="Proceedings of the 1996 VLSI Test Symposium",
        Pages="422-429", 
        Year="1996"}

@Inproceedings{Konu95,
        Title="Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks",
        Author="Haluk Konuk and F. Joel Ferguson and Tracy Larrabee",
        Organization="IEEE",
	Booktitle="Proceedings of the 1995 Design Automation Conference",
        Pages="345-351", 
        Year="1995"}

@Article{Konu96j,
        Title="Charge Based Fault Simulator for CMOS Network Breaks",
        Author="Haluk Konuk and F. Joel Ferguson and Tracy Larrabee",
	Key="Konuk",
	Journal=IEEETCAD,
        Pages="1555-1567", 
        Year="1996"}

@Inproceedings{Konu93,
        Title="Explorations of Sequential ATPG Using Boolean Satisfiability",
        Author="Haluk Konuk and Tracy Larrabee",
        Organization="IEEE",
	Booktitle="Proceedings of the 1993 VLSI Test Symposium",
        Pages="85-90", 
        Year="1993"}

@Article{Kuo90,
	Author="C. Kuo and T. Toms and B. Neel and J. Jelemensky and
E. Carter",
	Key="Kuo",
	Title="Soft-Defect Detection {(SDD)} Technique for a
High-Reliability {CMOS SRAM}",
	Journal=IEEEJSSC,
	Volume="25", Number="1",
	Pages="61-67", Month="February", Year="1990"}

@Article{Kuo93,
	Author="Sy-Yen Kuo",
	Key="Kuo",
	Title="{YOR}: A Yield-Optimizing Routing Algorithm by Minimizing Critical Areas and Vias",
	Journal=IEEETCAD,
	Volume="12", Number="9",
	Pages="1303-1311", Month="September", Year="1993"}
		
@InProceedings(Larr89itc,
    author="Tracy Larrabee",
    Key="Larrabee",
    title="Efficient Generation of Test Patterns Using {Boolean Difference}",
    BookTitle=PrITC, Organization="IEEE",
    year=1989,
    pages="795-801")

@inproceedings{Larrabee2,
 AUTHOR = "Larrabee, T.",
 TITLE = "A Framework for Evaluating Test Pattern Generation Strategies",
 BOOKTITLE = "Proceedings of the International Conference on
Computer Design",
 MONTH = Oct, YEAR = 1989,
 ORGANIZATION = "IEEE",
 NOTE="Also available as part of Digital Equipment Corporation Western
 Research Lab Research Report WRL-90/3"
}
    
@PhDThesis{Larr90dis,
	Author="Tracy Larrabee",
	Title="Efficient Generation of Test Patterns Using Boolean Satisfiability",
	School="Stanford University, Department of Computer Science",
	Month="February", number="STAN-CS-90-1302",
	Year="1990", Key="Larrabee"}

@Article{larrCAD92,
        Author="Tracy Larrabee",
        Title="Test Pattern Generation Using Boolean Satisfiability",
        Journal=IEEETCAD, Month="January", pages="4-15",
        Year="1992"}

@InProceedings{lee91,
        Author="Kuen-Jong Lee and Melvin A Breuer",
	Key="Lee",
        Title="Constraints for Using {IDDQ} Testing to Detect {CMOS} Bridging Faults",
	BookTitle= "Proceedings of the IEEE VLSI Test Symposium",
	Pages="303-308",
        Year="1991"}

@Article{lee92,
        Author="Kuen-Jong Lee and Melvin A Breuer",
        Title="Design and Test Rules for {CMOS} Circuits to Facilitate
{IDDQ} testing of Bridging Faults",
        Journal=IEEETCAD, Month="May", pages="659-670",
        Year="1992"}

@Article{lee94,
        Author="K.J. Lee and C.A. Mjinda and Melvin A Breuer",
        Title="A switch level Test Generation System for {CMOS} Combinational
	Circuits",
        Journal=IEEETCAD, Month="May", pages="625-637",
        Year="1994"}

@Article{LINE82,
	Author="J.R. Lineback",
	Key="Lineback",
	Title="Logic Simulation speeded with new special hardware",
        Journal="Electronics",
        Pages="45-46",
        Month="June 16",
        Year="1982"}
				 
@Article{Levi90
	,key="Levitt"
	,author="Marc E. Levitt and Jacob A. Abraham"
	,title="Physical Design of Testable {VLSI}:  Techniques and Experiments"
	,journal="IEEE Journal of Solid-State Circuits"
	,volume="25",year="1990",number="2",month="April",pages="474-481"}


@InProceedings{LAMO83,
	Author="P. Lamoureux and V.K. Agarwal",
	Key="Lamoureux",
	Title="Non-Stuck-At Fault Detection in {nMOS} Circuits by Region Analysis",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="129-137",
	Year="1983",
	Annote="Tests for diffusion shorts"}

@InProceedings{Lepe94,
	Author="D. Lepejian and J. Caywood and  A. Kablanian and  F. Joel Ferguson and A. Jee",
	Key="Lepejian",
	Title="An Automated Failure Analysis {(AFA)} Methodology for
Repeated Structures",
	Organization="IEEE",
	BookTitle= "Proceedings of the 1994 VLSI Test Symposium",
	Pages="319-324",
	Year="1994"}

@Article{LIU87,
	Author="D.L. Liu and E.J. McCluskey",
	Key="Liu",
	Title="Designing {CMOS} Circuits for Switch-Level Testability",
	Journal=IEEEDTC,
	Month="August",Year="1987",Volume="4",Number="4",pages="42-49"}

@InProceedings{Luka87,
	Author="W. Lukaszek and W. Yarbrough and K. Grambow",
	Key="Lukaszek",
	Title="{CMOS} Process Problem Debugging Using Complementary Defect Monitors",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="21-30", Year="1987"}

@Article{MA88,
	key="Ma",
	author="H.T. Ma and S. Devadas and A.R. Newton and A.
Sangiovanni-Vencentelli",
	Title="Test Generation for Sequential Circuits",
	Journal=IEEETCAD,
	Month="October",Year="1988",volume="CAD-7",number="10",
	Pages="1081-1091"}

@InProceedings{MALA82,
	Author="Y.K. Malaiya and S.Y.H. Su",
	Key="Malaiya",
	Title="A New Fault Model and Testing Technique for {CMOS} Devices",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="25-34", Year="1982",
	Annote="Leakage testing"}

@Inproceedings{MALA84,
	Title="Testing Stuck-On Faults in {CMOS} Integrated Circuits",
	Author="Yashwant K. Malaiya",
	Organization="IEEE",
	BookTitle= PrICCAD,
	Pages="248-250", Year="1984",
	key="Malaiya"}

@Article{MALY84,
	Author="W. Maly",
	Key="Maly",
	Title="Modeling of Point Defect Related Yield Losses for CAD of {VLSI} Circuits",
	Journal= PrICCAD,
	Month="November",
	Year="1984"}

@Inproceedings{MALY84a,
	Title="Systematic Characterization of Physical Defects for Fault Analysis of {MOS} {IC} Cells",
	Author="W. Maly and F.J. Ferguson and J. P. Shen",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="390-399", Year="1984",
	key="Maly"}

@Article{MALY85,
	key="Maly",
	author="W. Maly",
	Title="Modeling of Lithography Related Yield Losses for {CAD} of {VLSI} Circuits",
	Journal=IEEETCAD,
	Month="July",Year="1985",volume="CAD-4",number="3",pages="166-177"}

@TechReport{MALY86,
	Author="Wojciech Maly",
	Key="Maly", Address = CMUSRC, Number = "CMUCAD-86-11",
	Title="Probability Based Testing - Hopes and Realities",
	Institution="Carnegie Mellon University",Month="April",Year="1986"}

@Article{MALY86CAD,
	key="Maly",
	author="W. Maly and A.J. Strojwas and S.W. Director",
	Title="{VLSI} Yield Prediction and Estimation: A Unified Framework",
	Journal=IEEETCAD,
	Month="January",Year="1986",volume="CAD-5",number="1",pages="114-130"}
	
@inproceedings{MALY87
	,key="Maly"
	,author="Wojciech Maly"
	,title="Realistic Fault Modeling for {VLSI} Testing"
	,organization="IEEE"
	,booktitle= PrDAC
	,year="1987",pages="173-180"}
	% Photos of defects, Probability of faults, SSA not complete

@TechReport{MALY87t,
	Author="W. Maly and M.E. Thomas and J.D. Chinn and D.M. Campbell ",
	Key="Maly", Address = CMUSRC, Number = "CMUCAD-87-2",
	Title="Double-Bridge Test Structure for the Evaluation of Type, Size and Density of Spot Defects",
	Institution="Carnegie Mellon University",Month="February",Year="1987"}

@Inproceedings{Maly87itc,
	Title="Yield Diagnosis Through Interpretation of Tester Data",
	Author="W. Maly and B. Trifilo and R.A. Hughes and A. Miller",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="10-20", Year="1987",
	key="Maly"}

@Inproceedings{Maly88a,
	Title="Built-in Current Testing - Feasibility Study",
	Author="W. Maly and P. Nigh",
	Organization="IEEE",
	Booktitle= PrICCAD,
	Pages="340-343", Year="1988",
	key="Maly"}

@Inproceedings{Maly88b,
	Title="Testing Oriented Analysis of {CMOS} {IC}s with Opens",
	Author="W. Maly and P.K. Nag and P. Nigh",
	Organization="IEEE",
	Booktitle= PrICCAD,
	Pages="344-347", Year="1988",
	key="Maly"}

@Inproceedings{Maly89,
	Title="Process Monitoring Oriented {IC} Testing",
	Author="W. Maly and S.B. Naik",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="527-532", Year="1989",
	key="Maly"}

@Inproceedings{MAND84,
	Title="{CMOS} {VLSI} Challenges to Test",
	Author="K.D. Mandl",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="642-648", Year="1984",
	key="Mandl"}

@Inproceedings{MANT84,
	Title="On {CMOS} Totally Self-Checking Circuits",
	Author="S.R. Manthani and S.M. Reddy",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="866-877", Year="1984",
	key="Manthani"}

@Article{MANG84
	,key="Mangir"
	,author="T.E. Mangir"
	,title="Sources of Failures and Yield Improvement for {VLSI} and Restructurable Interconnects for {RVLSI} and {WSI}:  Part 1 - Sources of Failures and Yield Improvement for {VLSI}"
	,journal="Proceedings of the IEEE"
	,volume="72",year="1984",number="6",month="June",pages="690-708"}

@Inproceedings{MAO90,
	Title="{QUIETEST}: A Quiescent Current Testing Methodology for
Detectiong Leakage Faults",
	Author="W. Mao and R.K. Gulati and D.K. Goel and M.D. Ciletti",
	Organization="IEEE",
	BookTitle= PrICCAD,
	Pages="280-283", Year="1990",
	key="Mao"}

@Inproceedings{MATT87,
	Title="A C-testable Booth Multiplier, Designed for a Silicon
Compilation Environment",
	Author="L. Matterne and J. van Meerbergen and F. Beenker and
V. Mehra and J. Theunissen and  R. Segers",
	Organization="IEEE",
	BookTitle= PrICCD,
	Pages="354-357",
	Year="1987",
	key="Matterne"}
%  **

@inproceedings{Maxw91
	,key="Maxwell"
	,author="P.C. Maxwell and R.C. Aitken and V. Johansen and I. Chiang"
	,title="The effects of different test sets on
quality level prediction: When is 80% better than 90%?"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1991",pages="358-364"}


@inproceedings{Maxw92
	,key="Maxwell"
	,author="P.C. Maxwell and R.C. Aitken and V. Johansen and I. Chiang"
	,title="The effectiveness of IDDQ, functional and scan tests:
How many fault coverages do we need?"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1992",pages="168-177"}

@inproceedings{Maxw94
	,key="Maxwell"
	,author="P.C. Maxwell and R.C. Aitken and L. Huisman"
	,title="The Effect of Quality of Non-uniform Fault Coverage
and Fault Probability"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1994",pages="739-746"}

@inproceedings{MaxAit93
	,key="MaxAit93"
	,author="P. Maxwell and R. Aitken"
	,title="Biased Voting: a Method for Simulating {CMOS} Bridging
		  Faults in the Presence of Variable Gate Logic Thresholds"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1993",pages="63--72"}

@Article{MCCL85,
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	Year="1985",Month="April",
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@inproceedings{McCl88
	,key="McCluskey"
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	,title="{IC} Quality and Test Transparancy"
	,organization="IEEE"
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	,year="1988",pages="295-301"}

@inproceedings{MCDE81
	,key="McDermott"
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	,year="1981",pages="360-364"}

@Inproceedings{McGo97,
        Title="Incorporating Physical Design-For-Test into Routing",
        Author="Richard McGowen and F. Joel Ferguson",
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        Pages="685-693", 
        Year="1997"}

@InProceedings{McGo94E,
	Author="Richard McGowen and F. Joel Ferguson",
	Key="McGowen",
	Title="A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT",
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	BookTitle="European Design and Test Conference",
	Pages="371-375",
	Year="1994"}

@InProceedings{McGo94V,
	Author="Richard McGowen and F. Joel Ferguson",
	Key="McGowen",
	Title="Elimination of Undetectable Shorts During Channel Routing",
	Organization="IEEE",
	BookTitle="Proceedings of the VLSI Test Symposium",
	Pages="402-407",
	Year="1994"}

@TechReport{McGo93t1,
	Author="R. McGowen and F. Joel Ferguson",
	Key="McGowen", Address = "Computer Engineering Department",
	number ="UCSC-CRL-93-25",
	Title="A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT",
	Institution="University of California at Santa Cruz",
	Year="1993"}

@TechReport{McGo93t2,
	Author="R. McGowen and F. Joel Ferguson",
	Key="McGowen", Address = "Computer Engineering Department",
	number ="UCSC-CRL-93-48",
	Title="Elimination of Undetectable Shorts During Channel Routing",
	Institution="University of California at Santa Cruz",
	Year="1993"}

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@InProceedings{McEu91,
        Author="Steven D. McEuen",
	Key="McEuen",
        Title="{IDDq} Benefits",
	BookTitle= "Proceedings of the IEEE VLSI Test Symposium",
	Pages="285-290",
        Year="1991"}

@Article{MEI74,
	Author="K.C.Y. Mei",
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	Title="Bridging and Stuck-At Faults",
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@InProccedings{Merc84,
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      Key="Mercer",
      Title="Correlating Testability with Fault Detection",
      BookTitle=PrITC, Year="1984"}

@inproceedings{Midk93
	,key="Midkiff"
	,author="Scott F. Midkiff and S. Wayne Bollinger"
	,title="Classification of Bridging Faults in {CMOS} Circuits:
Experimental Results and Implications for Test"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1993",pages="112-115"}

@TechReport{Mill87,
	Author="S.D. Millman and E.J. McCluskey",
	Key="Millman", Address = CRC, Number = "87-20",
	Title="Detecting Bridging Faults With Stuck-at Test Sets",
	Institution="Stanford University",Month="December",Year="1987"}
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@Inproceedings{Mill88,
	Author="S.D. Millman and E.J. McCluskey",
	Key="Millman",
	Title="Detecting Bridging Faults With Stuck-at Test Sets",
	BookTitle=PrITC, Year="1988"}

@Inproceedings{Mill90,
	Author="S.D. Millman and E.J. McCluskey and J.M. Acken",
	Key="Millman",
	Organization="IEEE",
	Title="Diagnosising {CMOS} Bridging Faults with stuck-at fault dictionaries",
	Booktitle=PrITC,
	Year="1990",
	Pages="860-870"}

@Inproceedings{Mill91,
	Author="S.D. Millman and J.P. Garvey",
	Key="Millman",
	Organization="IEEE",
	Title="An Accurate Bridging Fault Test Pattern Generator",
	Booktitle=PrITC,
	Year="1991",
	Pages="411-418"}

@Article{Milo94,
	Author="Linda Milor and Alberto Sangiovanni-Vencentelli",
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analog circuits",
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	Pages="796-813", Month="June", Year="1994"}

@article{Naik93,
	Title="Failure Analysis of high-density {CMOS SRAM}s Using Realistic Defect Modeling and {Iddq} Testing",
	Author="S. Naik and F. Agricola and W. Maly", 
	Journal=IEEEDTC,
	Year="1993",Month="June",
	Volume="10",Number="2",
	Pages="13-23",
	key="Naik"}

@Inproceedings{Nigh89,
	Title="Layout-Driven Test Generation",
	Author="P. Nigh and W. Maly",
	Organization="IEEE",
	Booktitle= PrICCAD,
	Pages="154-157", Year="1989",
	key="Nigh"}

@Inproceedings{Ober91,
	Key="Oberle",
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Fault Simulator {RAMSIM}",
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	Booktitle=PrITC,
	Pages="548-555",
	Year="1991"}


@Article{OUST85,
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@InProceedings{ORTN77,
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@Article{PART81,
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	Year="1981",
	Annote="One step testability and fault location in log time"}

@InProceedings{Panc90,
	Author="Ashish Pancholy and Janusz Rajski and Larry McNaughton",
	Key="Pancholy",
	Title="Empirical Failure Analysis and Validation of Fault
Models in {CMOS} {VLSI}",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="938-947",
	Year="1990"}

@InProceedings{Perr92,
	Author="Roger Perry",
	Key="Perry",
	Title="{IDDQ} Testing in {CMOS} Digital {ASIC}s -- Putting it
all together",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="151-157",
	Year="1992"}

@InProceedings{PFIS82,
	Author="G.F. Pfister",
	Key="Pfister",
	Title="The Yorktown simulation engine: Introduction.",
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	BookTitle= PrDAC,
	Pages="51-54",
	Year="1982"}

@InProceedings{Pier95,
	Author="Alicja Pierzy\'{n}ska and Slawomir Pilarski",
	Key="Pierzynska",
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	Pages="123-131",
	Year="1995"}

@Inproceedings{Pome92,
	Author="Irith Pomeranz and S.M. Reddy",
	Key="Pomeranz",
	Title="On the generation of small dictionaries for fault location",
	Organization="IEEE",
	BookTitle= PrICCAD,
	Pages="272-279", Year="1992"}

@Article{Pome94a,
	Author="I. Pomeranz and S.M. Reddy",
	Key="Pomeranz",
	Title="An efficient Nonenumerative Method to Estimate the Path
delay fault coverage in Combinational Circuits",
	Journal=IEEETCAD,
	Volume="13",Number="2",
	Pages="240-250", Month="February", Year="1994"}

@Article{PRAS75,
	Author="B.A. Prasad and F.G. Gray",
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	Title="Multiple Fault Detection in Arrays of Combinational Cells",
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@InProceedings{Pram88,
	Author="A.K. Pramanick and S.M. Reddy",
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	Title="On the Detection of Delay Faults",
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	Pages="845-856",
	Year="1988"}

@Book{RAVI81,
	Author="K.W. Ravi",
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	Title="Imperfections and impurities in semiconductor silicon",
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	Year="1981"}

@InProceedings{RAJS87,
	Author=" R. Rajsuman and Y.K. Malaiya and A.P. Jayasumana",
	Key="Rajsuman",
	Title="On Accuracy of Switch-Level Modeling of Bridging Faults
in Complex Gates",
	Organization="ACM/IEEE",
	BookTitle= PrDAC,
	Pages="244-250",
	Year="1987"}
%  Shows that when Bulk is connected to source there may be problems
%  with switch level model.	***

@InProceedings{REDD83,
	Author="S.M. Reddy and M.K. Reddy and J.G. Kuhl",
	Key="Reddy",
	Title="On Testable Design for {CMOS} Logic Circuits",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="435-445",
	Year="1983"}

@InProceedings{REDD84,
	Author="S.M. Reddy and V.D. Agrawal and S.K. Jain",
	Key="Reddy",
	Title="A Gate Level Model for {CMOS} Combinational Logic Circuits with Application to Fault Detection",
	Organization="IEEE",
	BookTitle= PrDAC,
	Pages="504-509",
	Year="1984"}

@Article{Reno92,
	key="Renovell",
	author="M. Renovell and G. Cambon",
	Title="Electrical Analysis and Modeling of Floating-Gate Fault",
	Journal=IEEETCAD,
	Month="November",Year="1992",volume="CAD-11",number="11",
	pages="1450-1458"}

@Inproceedings{ROBI85,
	Author="S.H. Robinson and J.P. Shen",
	Key="Robinson",
	Title="Toward A Switch-Level Test Pattern Generation Program",
	Organization="IEEE",
	BookTitle= PrICCAD,
	Pages="39-41", Year="1985"}

@Article{Roca95
	,key="Roca"
	,author="M. Roca and A. Rubio"
	,title="Current Testability Analysis of Feedback Bridging
Faults in {CMOS} Circuits"
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	,volume="CAD-14"
	,year="1995", number="10"
	,month="October", pages="1299-1304"}

@Inproceedings{RODR91,
	Author="R. Rodr\'{i}guez-Montan\'{e}s and J.A. Segura and 
	V.H. Champac and J. Figueras and J.A. Rubio",
	Key=" Rodriguez-Montanes",
	Title="Current Vs. Logic Testing of Gate Oxide Short, Floating
Gate, and Bridging Failures in {CMOS}",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="510-519", Year="1991"}

@Inproceedings{RODR92,
	Author="R. Rodr\'{i}guez-Montan\'{e}s and E.M.J.G. Bruls and J. Figueras",
	Key=" Rodriguez-Montanes",
	Title="Bridging Defects Resistance Measurements in a {CMOS} Process",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="892-899", Year="1992"}

@TechReport{Roge94t,
	Author="Jeffrey Rogenski",
	Address = "Computer Engineering Department",
	number ="UCSC-CRL-94-21",
	Key="Rogenski",
	Title="`Characterization of Opens in Logic Circuits",
        Institution="University of California at Santa Cruz",Month="May",
	        Year="1994"}

@Inproceedings{Roge94,
	Author="Jeffrey Rogenski and  F. Joel Ferguson",
	Key="Rogenski",
	Title="Characterization of Opens in Logic Circuits",
	Organization="IEEE",
	BookTitle= PrASIC,
	Pages="358-361", Year="1994"}

@article{Roth66,
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 YEAR = 1966,
 PAGES = "278--291"
 }
      
@article{ROTH67,
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	key="Roth"}

@inproceedings{Rudn92
	,key="Rudnick"
	,author="Elizabeth Rudnick and W. Kent Fuchs and Janak Patel"
	,title="Diagnositic Fault Simulation of Sequential Circuits"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1992",pages="178-186"}

@article{RUSS80,
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	Year="1980", Month="October", Pages="46-57",
	key="Russel"}

@inproceedings{Ryan91
	,key="Ryan"
	,author="Paul Ryan and Shishpal Rawat and W. Kent Fuchs"
	,title="Two-Stage Fault Location"
	,organization="IEEE"
	,booktitle= PrITC
	,year="1991",pages="963-968"}

@InProceedings{Ryan93,
        Author="P.G. Ryan and W.K. Fuchs",
	Key="Ryan",
        Title="Addressing the Size Problem in Fault Dictionaries",
	BookTitle= "Proceedings of International Symposium for Testing and Fault Analysis",
	Pages="129-1133",
        Year="1993"}

@InProceedings{Ryan93iccad,
        Author="P.G. Ryan and W.K. Fuchs and Irith Pomeranz",
	Key="Ryan",
        Title="Fault Dictionary Compression and Equivalnece Class
Computation for Sequential Circuits",
	BookTitle= "Proceedings of International Conference on
Computer-Aided Design",
	Pages="508-511",
        Year="1993"}

@article{Sach97,
	Title="Open Defects in {CMOS RAM} Address Decoders",
	Author="Manoj Sachdev", 
	Journal=IEEEDTC,
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	Pages="26-33",
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@Article{Salu83,
	Author="K.K. Saluja and K. Kinoshita and H. Fujiwara",
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	Volume="C-32",Pages="1038-1046",Year="1983"}

@Inproceedings{Sara92,
	Title="Physical {DFT} for High Coverage of Realistic Faults",
	Author="M. Saraiva and P. Casimiro and M. Santos and J.T. Sousa and F. Goncalves and I Teixeira and J.P. Teixeira",
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	Booktitle= PrITC,
	Pages="642-647", Year="1992",
	key="Saraiva"}

@Inproceedings{Sarf89,
	Title="Hierarchical Test Pattern Generation Based on
High-Level Primitives",
	Author="T.M. Sarfert and R. Markgraf and E. Trischler and M.H. Schulz",
	Organization="IEEE",
	Booktitle= "PrITC",
	Pages="470-479", Year="1989",
	key="Sarfert"}
	
@Inproceedings{Savir83,
	Title="Random Pattern Testability",
	Author="J. Savir and G. Ditlow and P.H. Bardell",
	Organization="IEEE",
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	Pages="80-89", Year="1983",
	key="Savir"}
	
@article(Savi84Jan,
	author="J. Savir and G.S. Ditlow and P.H. Bardell",
	title="Random Pattern Testability",
	journal="{IEEE} Transactions On Computers",
	volume=33, number=1, month="Jan",
	year=1984,
	pages="79-90")

@Article{Savir84,
	Author="J. Savir and P. H. Bardell",
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	Volume="C-33",Number="6",Pages="467-474",Month="June",Year="1984"}

@Article{Savir94,
	Author="J. Savir and S. Patil",
	Key="Savir",
	Title="Broad-Side Delay Test",
	Journal=IEEETCAD,
	Volume="13",Number="8",Pages="1057-1065",Month="August",Year="1994"}

@InProceedings{Sawa92,
	Author=" K. Sawada and S. Kayano",
	Key="Sawada",
	Title="An evaluation of {I}ddq Versus Conventional Testing for
{CMOS} Sea-of-Gate {IC}'s",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="158-167",
	Year="1992"}

@Article{Sche72,
	Author="D.R. Schertz and G. Metze",
	Key="Schertz",
	Title="A New Representation for Faults in Combinational
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@Inproceedings{Schl90,
	Title="Detection of all Multiple Faults in two-dimensional
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	key="Schlag"}

@Article{Schl99,
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@TechReport{Schl95tr,
        Author="Martine Schlag and F. Joel Ferguson",
        Key="Schlag", Address = "Computer Engineering Department",
        number ="UCSC-CRL-95-30",
        Title="Detection of multiple faults in two-dimensional {ILA}s",
        Institution="University of California at Santa Cruz",Month="July",
        Year="1995"}


@Article{Schu88,
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	Month="January",Year="1988",volume="CAD-7",number="1",pages="126-137"}

@Inproceedings{Schu89,
	Title="Hierarchical Fault Simulation in Combinational Circuits",
	Author="M.H. Schulz and B.H. Seiss and F. Brglez",
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	Pages="33-40", Year="1989",
	key="Schulz"}

@Inproceedings{Corsi,
	Title="Assessing the quality level of digital {CMOS} {IC}s under the hypothesis of nonuniform distribution of fault probabilities",
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	Pages="72--78", Year="1996",
	key="Corsi"}

@Article{SESH65,
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@Inproceedings{Segu95,
	Title="A Detailed Analysis of {GOS} Defects in {MOS} Transistors: Testing Implications at the Circuit Level",
	Author="J. Segura and C. De Benito and A. Rubio and C.F. Hawkins",
	Organization="IEEE",
	Booktitle= "PrITC",
	Pages="544-551", Year="1995",
	key="Segura"}

@Inproceedings{Shen83,
	Title="Easily-Testable Array Multipliers",
	Author="J. P. Shen and F. J. Ferguson",
	Organization="IEEE",
	Booktitle= "PrFTCS",
	Pages="37-40", Year="1983",
	key="Shen"}

@Article{SHEN84,
	Author="J.P. Shen and F.J. Ferguson",
	Key="Shen",
	Title="The Design of Easily Testable {VLSI} Array Multipliers",
	Journal=IEEETC,
	Volume="C-33",Number="6",Pages="554-560",Month="June",Year="1984"}

@TechReport{SHEN85t,
	Author="J.P. Shen and W. Maly and F.J. Ferguson",
	Key="Shen", Address = CMUSRC, Number = "CMUCAD-85-51",
	Title="Inductive Fault Analysis of {nMOS} and {CMOS} Integrated Circuits",
	Institution="Carnegie Mellon University",Month="August",Year="1985"}
	
@Article{SHEN85,
	Key="Shen",
	Author="J.P. Shen and W. Maly and F.J. Ferguson",
	Title="Inductive Fault Analysis of {MOS} Integrated Circuits",
	Journal=IEEEDTC,
	Year="1985",Month="December",
	Volume="2",Number="6",
	Pages="13-26"}

@Book{Siew,
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	Title="The Theory and Practice of Reliable System Design",
	Publisher="Digital Press",
	Year="1982"}

@InProceedings{Sing95,
	Author=" Adit D. Singh and Haroon Rasheed and Walter W. Weber",
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	Pages="479-489",
	Year="1995"}

@Article{Sing93
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@InProceedings{Siva95,
	Author="Mukund Sivaraman and Andrzej Strojwas",
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	Pages="132-138",
	Year="1995"}

@InProceedings{Soden89,
	Author=" J.M. Soden and R.K. Treece and M.R. Taylor and C.F. Hawkins",
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	Organization="IEEE",
	BookTitle= PrITC,
	Pages="423-430",
	Year="1989"}

@inproceedings(Sode89Eur,
	author="Jerry M Soden and Charles F Hawkins",
	title="Electrical Properties and Detection Methods for {CMOS} {IC} Defects",
	booktitle="1st European Test Conference",
	year="1989",
	month="April")

@TechReport{Soden92T,
	Author="Jerry Soden and Charles Hawkins",
	Key="Soden",
	Title="{FMLEA} Project Work in Progress Report 7",
	Institution="Sandia National Laboratories",Month="January",Year="1992"}
	
@Article{SMIT79
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@Article{SMIT90
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@inproceedings(Sode89Eur,
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	year="1994")

@Article{SRID81,
	Author="T. Sridhar and J.P. Hayes",
	Key="Sridhar",
	Title="A Functional Approach to Testing Bit-Sliced Microprocessors",
	Journal=IEEETC,
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	Month="August",	Year="1981"}

@Article{STAP84,
	Author="C.H. Stapper",
	Key="Stapper",
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	Number="4",
	Pages="461-475",
	Month="July",
	Year="1984"}

@Article{STAP83b,
	Author="C.H. Stapper",
	Key="Stapper",
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	Month="November",
	Year="1983"}

@Article{STAP83
	,key="Stapper"
	,author="C.H. Stapper and F.M. Armstrong and K. Saji"
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@Article{STAP80
	,key="Stapper"
	,author="C.H. Stapper and A.N. McLaren and M. Dreckmann"
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% Shows metal defects most common ~70 percent, extra poly ~ 15%

@Inproceedings{STAR84,
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	key="Starke"}

@Inproceedings{Storey90,
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	key="Storey"}

@InProceedings{Syrz87,
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	Organization="IEEE",
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	Pages="148-157",
	Month="September",
	Year="1987",
	Key="Syrzycki"}
% Gate Oxide shorts (current and logical effects).

@InProceedings{SZYG72,
	Author="S.A. Szygenda",
	Key="Szygenda",
        Title="{TEGAS} 2 - Anatomy of a General Purpose Test Generation and Simulation System for Digital Logic",
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	Month="June", Year="1972"}


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@InProceedings{TIMO83,
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	Year="1983",
	Key="Timoc"}

@Article{THAT80,
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@InProceedings{TREU85,
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	Year="1985"}

@InProceedings{Tsuk79,
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	Year="1976"}

@InProceedings{TURN85,
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	Year="1985"}

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	Year="1985"}

@Article{Walk86,
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	Year="1986", Key="Walker"}

@PhDThesis{Walk86p,
	Author="H. Walker",
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	School="Carnegie Mellon University, Computer Science Department",
	Month="July",
	Year="1986", Key="Walker"}

@Article{Wall93,
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	Journal= PrITC,
	Year="1993"}

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	Year="1973", Key="Williams"}

@Article{Will81,
	Author="T.W. Williams and N.C. Brown",
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	Volume="C-30", Number="12",
	Pages="987-988", Month="December",
	Year="1981", Key="Williams"}

@Article{Will82,
	Author="T.W. Williams and K.P. Parker",
	Title="Design for Testability - A Survey",
	Journal=IEEETC,
	Volume="C-31", Number="1",
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	Year="1982", Key="Williams"}

@Inproceedings{WOOD87,
	Title="Empirical Results on Undetected {CMOS} Stuck-Open Failures",
	Author="B.W. Woodhall and B.D. Newman and A.G. Sammuli",
	Organization="IEEE",
	Booktitle= PrITC,
	Pages="166-170", Year="1987",
	key="Woodhall"}
% Experiment - Only 0.121% stuck-open escape rate for 100\% SSA test.

@Article{Wu90,
	Author="C.-W. Wu and P.R. Cappello",
	Title="Easily Testable Iterative Logic Arrays",
	Journal=IEEETC,
	Volume="C-39", Number="5",
	Pages="640-652", Month="May",
	Year="1990", Key="Wu"}

@InProceedings{Xu82,
	Author="S. Xu and S.Y.H. Su",
	Key="Xu",
	Title="Testing Feedback Bridging Faults Among Internal, Input and Output Lines by Two Patterns",
	Organization="IEEE",
	BookTitle="Proc. of Int. Conf. on Circ. and Comp.",
	Pages="214-217",
	Year="1982"}

@InProceedings{ULRI73,
	Title="The concurrent simulation of nearly identical digital networks",
	Author="E.G. Ulrich and T. Baker",
	Organization="IEEE",
	BookTitle= PrDAC,
	Pages="145-150",
	Year="1973",
	key="Ulrich"}

@article{Waic87,
	Title="Transistion Fault Simulation",
	Author="J. Waicukauski and E. Lindbloom and B.K. Rosen and
V.S. Iyengar", 
	Journal=IEEEDTC,
	Year="1987",Month="April",
	Volume="4",Number="2",
	Pages="32-38",
	key="Waicukauski"}

@InProceedings{Wisc93,
	Author="Paul Wiscombe",
	Key="Wiscombe",
	Title="A Comparison of stuck-at fault coverage and {Iddq}
Testing on Defect levels",
	Organization="IEEE",
	BookTitle= PrITC,
	Pages="293-299",
	Year="1993"}

@InProceedings{YAJI81,
	Author="S. Yajima and T. Aramaki",
	Key="Yajima",
	Title="Autonomously Testable Programmable Logic Arrays",
	Organization="IEEE",
	BookTitle= PrFTCS,
	Pages="41-43",
	Year="1981"}

% * References D and T Shen,Maly,Ferguson paper.
% ** References C-testability paper.
% *** References Graph Theory paper.
\end{thebibliography}