Publications

2005

uComplexity: Estimating Processor Design Effort, Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskmap, Josep Torrellas, and Jose Renau. 38th International Symposium on Microarchitecture (MICRO), November 2005.
POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure, Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas. The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (PAC2), September 2005.
Thread-Level Speculation on a CMP Can Be Energy Efficient Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005.
Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005.

2004

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, IEEE TCCA Computer Architecture Letters (TCCA), Dec 2004.
Chip Multiprocessors with Speculative Multithreading: Design for Performance and Energy Efficiency. Jose Renau, PhD Thesis, Aug 2004.

2003

Positional Adaptation of Processors: Application to Energy Reduction, Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Computer Architecture (ISCA), June 2003.
Programming a Parallel Intelligent Memory System, Basilio B. Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas, Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2003.

2002

Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors, Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois), 35th International Symposium on Microarchitecture (MICRO), November 2002. ( slides)
Energy-Efficient Hybrid Wakeup Logic , Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Low Power Electronics and Design (ISLPED), August 2002.
A Framework for Dynamic Energy Efficiency and Temperature Management , Michael Huang, Jose Renau, and Josep Torrellas Journal on Instruction Level Parallelism (JILP), 2002.

2001

Profiled-Based Energy Reduction for High-Performance Processors , Wei Huang, Jose Renau, and Josep Torrellas, 4th ACM Workshop on Feedback-Directed and Dynamic Optimization, December 2001
Energy/Performance Design of Memory Hierarchies for Processor-In-Memory Chips , Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 2nd Workshop on Intelligent Memory Systems, November 2000, Lecture Notes in Computer Science(Vol. 2107) by Springer-Verlag, 2001
Cache Decomposition for Energy-Efficient Processors , Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas , International Symposium on Low Power Electronics and Design (ISLPED), August 2001. ( slides)

2000

A Framework for Dynamic Energy Efficiency and Temperature Management, Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 33rd International Symposium on Microarchitecture (MICRO), December 2000.
Memory Hierarchies in Intelligent Memories: Energy/Performance Design, Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, Ninth Workshop on Scalable Shared Memory Multiprocessors, June, 2000. ( slides)
FlexRAM architecture design parameters , Seung-Moon Yoo, Wei Huang, Jose Renau, and Josep Torrellas, Technical Report 1584, October 2000

Earlier

Memory Hierarchies in Intelligent Memories: Energy/Performance Design Jose Renau, MS Thesis, University of Illinois December, 1999
Systemas Alternativos de Interconnexion. El IEEE1284 en Linux., Jose Renau, MS Thesis, Ramon Llull University, 1997.

2005	uComplexity: Estimating Processor Design Effort, Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskmap, Josep Torrellas, and Jose Renau. 38th International Symposium on Microarchitecture (MICRO), November 2005. POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure, Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas. The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (PAC2), September 2005. Thread-Level Speculation on a CMP Can Be Energy Efficient Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005. Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005.
2004	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, IEEE TCCA Computer Architecture Letters (TCCA), Dec 2004. Chip Multiprocessors with Speculative Multithreading: Design for Performance and Energy Efficiency. Jose Renau, PhD Thesis, Aug 2004.
2003	Positional Adaptation of Processors: Application to Energy Reduction, Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Computer Architecture (ISCA), June 2003. Programming a Parallel Intelligent Memory System, Basilio B. Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas, Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2003.
2002	Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors, Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois), 35th International Symposium on Microarchitecture (MICRO), November 2002. ( slides) Energy-Efficient Hybrid Wakeup Logic , Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Low Power Electronics and Design (ISLPED), August 2002. A Framework for Dynamic Energy Efficiency and Temperature Management , Michael Huang, Jose Renau, and Josep Torrellas Journal on Instruction Level Parallelism (JILP), 2002.
2001	Profiled-Based Energy Reduction for High-Performance Processors , Wei Huang, Jose Renau, and Josep Torrellas, 4th ACM Workshop on Feedback-Directed and Dynamic Optimization, December 2001 Energy/Performance Design of Memory Hierarchies for Processor-In-Memory Chips , Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 2nd Workshop on Intelligent Memory Systems, November 2000, Lecture Notes in Computer Science(Vol. 2107) by Springer-Verlag, 2001 Cache Decomposition for Energy-Efficient Processors , Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas , International Symposium on Low Power Electronics and Design (ISLPED), August 2001. ( slides)
2000	A Framework for Dynamic Energy Efficiency and Temperature Management, Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 33rd International Symposium on Microarchitecture (MICRO), December 2000. Memory Hierarchies in Intelligent Memories: Energy/Performance Design, Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, Ninth Workshop on Scalable Shared Memory Multiprocessors, June, 2000. ( slides) FlexRAM architecture design parameters , Seung-Moon Yoo, Wei Huang, Jose Renau, and Josep Torrellas, Technical Report 1584, October 2000
Earlier	Memory Hierarchies in Intelligent Memories: Energy/Performance Design Jose Renau, MS Thesis, University of Illinois December, 1999 Systemas Alternativos de Interconnexion. El IEEE1284 en Linux., Jose Renau, MS Thesis, Ramon Llull University, 1997.