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News Blog |
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| 2009-02-24 |
Measuring and Modeling Variability using Low-Cost FPGAs paper accepted Michael Brown, Cyrus Bazeghi, Matthew Guthaus and Jose Renau, Poster at the International Symposium on Field-Programmable Gate Arrays | 2008-07-16 |
Understanding bug fix patterns in verilog paper accepted Sangeetha Sudakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau, Fith International Workshop on Mining Software Repositories, May 2008. | 2008-06-18 |
Implementation of a Power Efficient High Performance FPU for SCOORE paper accepted Wael Ali Ashmawi, John Burr, Abhishek Sharma, Jose Renau, Workshop on Architectural Research Prototyping (WARP), held inconjunction with ISCA-35, June 2008. | 2008-06-09 |
New thermal page This page shows several of the thermal measurements performed by the MASC group | 2008-06-08 |
New PhD Students (Gabriel Southern and Ehsan Ardestani) Both would start in Fall 08 | 2008-09-24 |
Therminic conference call for papers Papers are due on 2008-03-30. More information on Therminic International Workshop on Thermal inverstigations of ICs and Systems | 2008-01-22 |
ICCAD conference call for papers Papers are due on 2008-04-14. More information on ICCAD International Conference on Computer-Aided Design | 2008-04-10 |
NSF CRI Infrared Equipment ($275K) NSF Infrastructre award to purchase the IR measurement setup. | 2008-01-12 |
New PhD Student (Alamelu) Alamelu will start her PhD once she finishes the MS. | 2008-04-01 |
Measuring Power and Temperature from Real Processors paper accepted Francisco-Javier Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau, The Next Generation Software (NGS) Workshop (NGS08) held in conjunction with IPDPS, April 2008. | 2008-03-01 |
WACI paper accepted uDSim, a Microprocessor Design Time Simulation Infrastructure. Sangeetha Sudhakrishnan, Francisco-Javier Mesa-Martinez, Jose Renau, Wild and Crazy Ideas VI (WACI) held in conjunction with ASPLOS, March 2008. uDSim | 2008-01-10 |
Processor Verification with hwBugHunt paper accepted Sangeetha Sudhakrishnan, Liying Su, and Jose Renau, IEEE International Symposium on Quality Electronic Design (ISQED), March 2008. First Sangeetha's paper, congratulations. | 2008-02-01 |
Springer paper accepted System and Processor Design Effort Estimation, Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau, Springer Research Trends in VLSI and Systems on Chip. Mostly Cyrus thesis. | 2008-01-10 |
nVIDIA Gift ($70K) Gift to support thermal projects at the MASC group. | 2007-10-10 |
NSF CSR Infrared Thermal Measurement ($300K) Three years NSF grant for the thermal measurement infrastructure setup. | 2007-10-04 |
PACT conference call for papers Papers are due on 2008-03-20. More information on PACT Parallel Architectures and Compilation Techniques (PACT) | 2007-08-23 |
New BLOG for the MASC group | 2007-09-10 |
Effective Optimistic-Checker Tandem Core Design Through Architectural Pruning paper accepted Francisco J. Mesa-Martinez and Jose Renau, 40th International Symposium on Microarchitecture (MICRO), December 2007. Not a bad year for Javi, he has an ISCA and a MICRO. | 2007-08-10 |
Estimating Design Time for System Circuits paper accepted Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau, 15th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), October 2007. | 2007-07-01 |
Xilinx Equipment Donation We have licenses to the latest Xilinx software tools. | 2007-08-15 |
ISCA conference call for papers Papers are due on 2007-11-09. More information on ISCA First-tier conference on computer architecture. This year, it is held on China. | 2007-06-01 |
Javi Graduated His thesis introduces a new methodology to improve processor efficiency by reducing the size of the codebase for a processor design in order to manage increases in complexity and extract further performance from already existing design. Based on this methodology he introduces a novel Tandem architecture which combines a complex out-of-order core, that has some of it underutilized functionality removed, with a verified simpler in-order core that guarantees forward progress whenever excised functionality from the complex processor is exercised. | 2007-05-10 |
NASA/UARC "Radiation Tolerant FPGA Processor" ($25K) Grant to continue supporting the development of the SCOORE project. | 2007-05-01 |
Power Model Validation Through Thermal Measurements paper accepted Francisco J. Mesa-Martinez, Joseph Nayfach-Battilan, and Jose Renau, International Symposium on Computer Architecture (ISCA), June 2007. | 2007-05-01 |
Measuring Performance, Power, and Temperature from Real Processors paper accepted Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, and Jose Renau, 1st Workshop on Experimental Computer Science (FCRC), June 2007. | 2007-02-02 |
SUN OpenSPARC Center of Excellence at Santa Cruz Sun created the first ever OpenSPARC Center of Excellence at UCSC. | 2007-02-01 |
SUN Academic Excellence Grant ($110K) Sun donated $110K equipment to our group. Thanks Sun for this wonderful gift. | 2006-09-01 |
SEED Scalable, Efficient Enforcement of Dependences paper accepted Francisco J. Mesa-Martinez, Michael C.Huang, and Jose Renau, 15th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2006. | 2006-06-01 |
Printed Circuit Board Layout Time Estimation paper accepted Cyrus Bazeghi and Jose Renau, 7th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-33, June 2006. | 2006-06-01 |
SCOORE Santa Cruz Out-of-Order RISC Engine, FPGA Design Issues paper accepted Francisco J. Mesa-Martinez, Abhishek Sharma, Andrew W. Hill, Carlos A. Cabrera, Cyrus Bazeghi, Hari Kolakaleti, Joseph Nayfach, Keertika Singh, Kevin S. Halle, Matthew D. Fischler, Melisa Nuñez, Sangeetha Nair, Suraj Narender Kurapati, Wael Ali Ashmawi, and Jose Renau , Workshop on Architectural Research Prototyping (WARP), held inconjunction with ISCA-33, June 2006. | 2006-05-01 |
IES Berkeley/France Fund ($9K) This small grant is shared with Albert Cohen from INRIA. The objective is to establish a collaboration between the two centers. | 2006-03-01 |
Using Checkpoint-Assisted Value Prediction to Hide L2 Misses paper accepted Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, ACM's Transactions on Architecture and Code Optimization (TACO), March 2006. | 2006-03-01 |
POSH A TLS Compiler that Exploits Program Structure paper accepted Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas, ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), March 2006. | 2006-02-01 |
Special Research Grant from UCSC ($12K) Small explorative grant to rent/purchase equipment to get preliminary results on thermal projects. | 2006-01-20 |
NASA/UARC "Checkpointed Fault Tolerant FPGA Systems" ($50K) Grant to support the development of the SCOORE project. | 2006-01-20 |
NSF CAREER ($400K) The goal of this CAREER is to understand, estimate, and reduce processor design complexity. To do so, the PI plans to develop uComplexity metrics to understand and estimate processor design complexity. The uComplexity metric consist of three main parts, namely a procedure to account for the contributions of the different components in the design, accurate statistical regression of experimental measures using a nonlinear mixed-effects model, and a productivity adjustment to account for the productivities of different teams. Once the metrics are developed, the we plan to develop new approaches to reduce processor design complexity. | 2006-01-01 |
Energy-Efficient Thread-Level Speculation on a CMP paper accepted Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas, IEEE Micro Special Issue Micro's Top Picks from Computer Architecture Conferences, January-February 2006. | 2005-11-01 |
uComplexity Estimating Processor Design Effort paper accepted Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau. 38th International Symposium on Microarchitecture (MICRO), November 2005. | 2005-10-01 |
Sun grid donation of 100K CPU hours Sun has donated 100K CPU on their sungrid project. We are not going to have CPU constraints the next year. | 2005-10-01 |
Sun Niagara donation Sun donated a Niagara (T1) machine to our group. Thanks for the support. | 2005-09-01 |
POSH A Profiler-Enhanced TLS Compiler that Leverages Program Structure paper accepted Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas. The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), September 2005. | 2005-06-01 |
Thread-Level Speculation on a CMP Can Be Energy Efficient paper accepted Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005. | 2005-06-01 |
Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors Microarchitecture and Compilation paper accepted Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005. | 2005-04-01 |
Altera Equipment Donation We have floating Quartus licenses. | 2004-12-01 |
CAVA Hiding L2 Misses with Checkpoint-Assisted Value Prediction paper accepted Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, IEEE TCCA Computer Architecture Letters (TCCA), Dec 2004. | 2004-10-01 |
HPCS Complexity Management (Prime DoD/DARPA, Agency UIUC) Small grant to purchase some equipment. | 2004-07-01 |
UCSC Faculty Development award ($2K) First small grant for our group. | 2003-09-01 |
Managing Multiple Low-Power Adaptation Techniques The Positional Approach paper accepted Michael Huang, Jose Renau and Josep Torrellas, Sidebar on Special Issue on Power-Aware Computing, (IEEE Computer), December 2003. | 2003-06-01 |
Positional Adaptation of Processors Application to Energy Reduction paper accepted Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Computer Architecture (ISCA), June 2003. | 2003-06-01 |
Programming a Parallel Intelligent Memory System paper accepted Basilio B. Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas, Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2003. | 2002-11-01 |
Cherry Checkpointed Early Resource Recycling in Out-of-order Microprocessors paper accepted Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois), 35th International Symposium on Microarchitecture (MICRO), November 2002. | 2002-08-01 |
Energy-Efficient Hybrid Wakeup Logic paper accepted Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Low Power Electronics and Design (ISLPED), August 2002. | 2002-06-01 |
A Framework for Dynamic Energy Efficiency and Temperature Management paper accepted Michael Huang, Jose Renau, and Josep Torrellas Journal on Instruction Level Parallelism (JILP), 2002. | 2001-12-01 |
Profiled-Based Energy Reduction for High-Performance Processors paper accepted Wei Huang, Jose Renau, and Josep Torrellas, 4th ACM Workshop on Feedback-Directed and Dynamic Optimization, December 2001. | 2001-06-01 |
Energy/Performance Design of Memory Hierarchies for Processor-In-Memory Chips paper accepted Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 2nd Workshop on Intelligent Memory Systems, November 2000, Lecture Notes in Computer Science(Vol. 2107) by Springer-Verlag, 2001. | 2001-08-01 |
Cache Decomposition for Energy-Efficient Processors paper accepted Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas , International Symposium on Low Power Electronics and Design (ISLPED), August 2001. | 2000-12-01 |
A Framework for Dynamic Energy Efficiency and Temperature Management paper accepted Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 33rd International Symposium on Microarchitecture (MICRO), December 2000. | 2000-06-01 |
Memory Hierarchies in Intelligent Memories Energy/Performance Design paper accepted Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, Ninth Workshop on Scalable Shared Memory Multiprocessors, June, 2000. |