Downloading A Design into the Xilinx FPGA

Your starting point is a design that you have tested to your satisfaction. If you haven't thoroughly tested your design it is not likely to work. It is remarkably easy to implement and download a design using the Xilinx software and FPGA. Implementing a design is accomplished with the following steps:

• Add Input/Ouput Buffers into your design
• Wire the Xilinx chip power and ground
• Wire the downloading cable
• Implement the design
• Download the design
• Rewire the Xilinx Chip

Add Input/Output Buffers to Your Design.

Look for the parts IBUF and OBUF in the parts library. Implement these buffers in series with any signal that is coming in or out of the chip. For example if I wanted to implement the design of a 3 input AND gate my schematic would look like:

These are used to match the outside TTL levels with the more sensitive internal logic of the Xilinx. It is a good idea to simulate your design one final time to make sure nothing has changed.

Wire the Xilinx Power and Ground:

The Xilinx should be handled with care. The part is static sensitive and should be kept inside your parts envelope with the pins in the foam when you are not using it. Insert the 84 pin IC socket into the protkit utilizing the numbers in the plug board. Pin 1 of the chip is closest to the marking PA-1, then the pins are numbered in the usual order. If you take out the plastic boxes from the lab kit then you can close the lid with the Xilinx plugged in , which reduces the stress on the pins from insertion/removal. Now you can use the data sheet to wire the VCC and GND in eight separate locations.

Wire the Downloading Cable:

Insert the 6 pin 'stake header' in a convenient place in the plug board. Wire the communication signals from the Xilinx to the stake header using the following chart and the Xilinx data sheet.

You will not use the violet or white cables. It is a very good idea to preserve the color conventions from the Xilinx to the stake header to avoid confusion. Now connect the cable from the computer to the stake header, and you ready to configure and download.

Implement the Design:

Run the design by clicking the 'implementation' icon. Make sure that the correct part number is chosen. If you cannot select 4003EPC84 you may need to change your 'project type' from the file menu then select the 4000E family. In the implementation stage the software will automatically translate, map , route, and configure your design so that it can be downloaded. During the implementation, the Xilinx software will assign pins to your input and output signals.

The software will notify your when your design is implemented correctly. If your design does not work then you can find the errors by looking at different reports from the report browser. The report browser can be accessed from the project manager.

Download the Design:

Now if everything has worked so far you are ready to download the design into the Xilinx chip. You can launch the 'Hardware Debugger', from the project manager. Select 'Download Design' from the 'Download' menu to send your design to the chip.

Rewire the Xilinx:

One of the reports you can view from the report browser is the 'pad report'. This tells you how to reconnect the Xilinx to the input and outputs of your design. You might have to disconnect the pins to the stake header as the IO pins might be assigned to one of the communications pins. Another useful option is the 'lock pins' option from the project manager. This option will preserve the pin assignments should you have to implement your design again.

Remember that the Xilinx is volatile, meaning that it will forget what was downloaded into it once the power is turned off.

Now test your design and hopefully everything works!