CMPE 100 Lab #7
Report due by midnight Tues May 25

Description

For this lab you will design a simple finite-state machine to use as a controller, along with a counter to use as a timer. The idea for the lab comes from a VLSI design textbook by Mead and Conway. The machine you will design is a simplified version of a traffic-light controller (real traffic-light controllers have to handle many different sensors, traffic phases, and timers, and the control algorithm is usually done in software nowadays). Foo is a growing city on a major highway. Because of newly built factory outlet stores, the traffic on the highway has become unbearable, and the local farmers are pressuring the city counsel for changes. The farmers are demanding a traffic light so that they can cross the highway without having to wait so long. The Foo city counsel doesn't have much money, so it is willing take a chance on you. Can you design a traffic light controller for them? Here are the design requirements:
  1. The intersection is 4-way where the highway and farm road cross, so there are four traffic lights total, which are controlled in pairs.
  2. One direction (highway or farm) must be red, the other may be yellow or green.
  3. In any given direction, the lights always go from green to yellow to red to green (no yellow after red).
  4. The farm road has sensors in either direction to indicate if a car is waiting to cross the highway.
  5. The highway light should usually be green unless the farm road sensors are triggered. When the farm road sensors are triggered, the farm road should soon get a green light.
  6. When the farm road has a green light, it can only stay green for a maximum time, before it yields to the highway.
  7. Whenever the highway light turns green, it will stay green for a minimum amount of time before it responds to the sensor again.
  8. The length of the yellow light is determined by a selectable value.

Lab 7 prelab

  1. You must use a loadable, synchronous down counter to generate the timing signals in your design. Figure out how to use a loadable, down counter which will assert a signal after its done counting. Your counter will load a timing value, then count down to zero where it generates a DONE signal.
  2. You will probably need only one timer, if you arrange for it to be loaded with different values as needed---we believe this design only needs one thing to be timed at a time.
  3. Generate a block diagram showing your Mealy machine, and the interface to the counter. Your inputs (the farm road sensors) will be sampled at the clock rate, meaning that these values need to be captured in a register.
  4. Draw the state diagram for your finite-state machine.
  5. Figure out how many states there are, and what will be used for the state encodings.
  6. Generate a complete functional spec for your main logical block (use truth tables, Karnaugh maps, logic functions, or whatever specification method seems most natural for the problem).

Lab Work

System Design

  1. Create the appropriate counter by modifying a Xilinx library part. The following .pdf has helpful info about the Xilinx library (Warning--this is 5Mbytes long):

    http://www.xilinx.com/support/sw_manuals/libguide.pdf.

    The counter you will create will be:

    There is no part in the Xilinx library that meets all of these design specs exactly, but you can use the counter with the asynchronous clear (CC16CLED), then tie the clear input to the appropriate constant value, so that the counter is never cleared.

  2. You need to generate an event on two different time periods: TL and TS. TL is the maximum length of time for the farm road green, and the minimum value for the highway green. TS is the length of time for the yellow light. These will be 6-bit values (most significant of your 16-bit counter), and should be stored into registers. In addition, the values in these registers can be input by the user, so you will need a selector to write to either register. Since you are using a loadable down counter, TL or TS will be the selected value to be loaded into the counter. (Small bonus points: allow three times, so that the maximum farm green and minimum highway green can be different.)

  3. The Farm road sensors are sampled at the clock rate. This means that the sensor signal will go through a D flip-flop before it reaches your logic block.

  4. The total inputs to your system are:

    The outputs should be:

Design Capture/Device Programming

  1. Input your design into the Xilinx software and simulate.
  2. Download your design and show the working circuit to the T.A.

Report

By now you should know how to write a good report and what to include. Document the design process with whatever you feel is necessary. Think of your audience as the engineer who will have to make some modifications to the design in a year or two when the requirements changes slightly---that is far more realistic than writing to the TA or professor.

Submit your lab report as a postscript (or HTML) file by e-mailing it as an attachment to the TA of your lab section. Also, submit the prelab for next week's lab assignment.


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Questions about page content should be directed to

Kevin Karplus
Computer Engineering
University of California, Santa Cruz
Santa Cruz, CA 95064
USA
karplus@cse.ucsc.edu
1-831-459-4250