CMPE 100 Lab #6
Report due by midnight May 14

Description

Here are some common waveforms:

The basis of the function generator is a "phase oscillator" that generates a sawtooth. A phase oscillator consists of a register holding the PHASE (usually interpreted as an unsigned number, though this is not essential), to which the input FREQUENCY is added on each clock cycle. This creates a ramp, whose slope is the frequency, until the adder overflows, at which time it wraps around to make a sawtooth waveform. This phase oscillator is at the heart of music synthesizers, whether implemented in hardware or software.

Mathematically, the function you are computing on each cycle is:

where w is the largest integer representable in the PHASE register. That means p(t) = (sum_(i< t) f(i)) % w. If the frequency input is constant, this is just p(t) = (f*t) %w. In t clock cycles, the sawtooth will have wrapped around f*t/w times, so the frequency of the output is f/w times the clock frequency.

Note that you can keep the PHASE and the FREQUENCY to higher precision than your output DAC---just use the top 8 bits of the PHASE register to determine the output.

Lab 6 prelab

1. Read and understand the use of a D/A converter, and look at the data sheet for the chip that we will use to understand the interface from the FPGA to the D/A. When you use the D/A converter you will tie pins 16 and 14 together. What does this do?
2. Figure out how to make a 12-bit phase oscillator which is modeled by the equations above. You can have the frequency be fewer than 12 bits (add to the lower-order bits of the phase).
3. Generate a 'top-level' block diagram showing all of the important functional blocks in your function generator. Your block diagram should include:
   • A register
   • An adder
   • Functional blocks (not logic gates) for each different output function
   • Logic for switching the output
   • The interface to the D/A chip

Lab Work

Hardware/Software

1. Finalize your block diagram by determining the logic you will need to fill in the hierarchy blocks.
2. Enter your design into the Xilinx software and simulate.
3. Download your design and interface to the D/A chip.
4. Now use the scope to view the different functions, and show the working function generator to the TA. You should be running the clock at about 500 kHz to see the output clearly.
5. How does the input clock signal relate to the frequency of the output waveform for different switch settings? For a known clock frequency, what is input value that will give you the maximum frequency output of your function generator?

Report

In an industrial setting, you would probably include in your lab notebook photographs (or printout from a digital scope) of the most important waveforms. Since we don't have scope cameras available for you, sketch the important waveforms in your lab notebook and indicate what measurements you made from them.

Submit your lab report as a postscript (or HTML) file by e-mailing it as an attachment to the TA of your lab section. Also, submit the prelab for next week's lab assignment.

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