CMPE 100 Lab #3
Report due by midnight April 23

Description

The ALU you will design will be able to add or subtract two four-bit binary numbers. It will have two four-bit data inputs, A= (a3, a2, a1, a0) and B=(b3, b2, b1, b0), a four-bit result, R = (r3, r2, r1, r0), and a single-bit carry-out (Cout), which would be r4 if R were a 5-bit number. It will also have a "subtract" control input, S, that will be 0 for addition and 1 for subtraction. Assume that the inputs and outputs of the ALU represent twos-complement numbers. You have to get the subtraction right whether the answer is positive or negative---as long as the difference is representable in the 4-bit word.

Lab 3 prelab

1. Devise a scheme to subtract by adding. Describe the scheme in words and in logic equations.
2. What is the logic equation for the Cout signal (you may express it in terms of intermediate signal names, if you show how those signals are computed)?
3. Draw hierarchical block diagrams of your 4-bit circuit, showing how the 4-bit sum is generated from single-bit blocks, and showing how a single-bit block does the computation. You may use a full-adder cell as a component in the block diagram.

Lab Work

Software and Simulation:

1. Design a circuit that can just do the addition. This is called a 4-bit full adder. In binary, subtraction is accomplished by negating one number (finding its 2's complement) and then adding. To find the 2's complement of a number, invert all of its bits and then add one to it. Try a few examples to see how it works. Now find a simple way to introduce the select input into your full adder to allow it to add and subtract. (The conversion from 4-bit adder to 4-bit adder+subtractor will require only one additional IC). You can design your circuit with any gates you want, but don't use any of the larger elements like adders, decoders, multiplexers, etc.
2. Encapsulate your full-adder circuit from lab 2 in a new logic block using the hierarchy tool in Xilinx. This will create a new part which you can use whenever you want so you don't have to redraw the 1 bit circuit.
3. Make a 4-bit circuit by chaining together four copies of your 1-bit circuit by their carry inputs and outputs. Simulate the circuit for all possible combinations of inputs.
4. For extra credit add an overflow error output (Ov) for the 4-bit ALU that will be a logic 1 if the ALU result is NOT correctly representable in 4 bits.

Hardware:

1. The hardware part of this lab is to build a two-bit full adder/subtractor in your lab kit and demonstrate it to the TA. Each lab partner should build one bit with as little help as possible from his/her partner. Demonstrate both the two-bit physical circuit and the four-bit simulation to the TA.

Report

Submit your lab report as a postscript (or HTML) file by e-mailing it as an attachment to the TA of your lab section. Also, submit the prelab for next week's lab assignment.

Prelab for Lab 4

1. Work out the correct definition for the overflow bit and provide a logic formula for it.
2. You and your partner should generate a complete 'top level' block diagram of the enhanced ALU and register. This diagram should explicitly show the major functional hierarchy blocks, their interconnections, as well as the multiplexer and the output buffer (the register). It is probably best to do the hierarchy as a bit-slice design, so that you can just array n "alu_slice" cells to get an n-bit alu.

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