CMPEE 100 Lab #2
Report due by midnight April 16
Description
In this lab you will design and build a circuit called a full adder,
which is a fundamental building block in computer arithmetic circuits.
The circuit will sum three bits (each with weight 1) and display the
2-bit output.
Lab 2 prelab
You will be designing a circuit called a full adder, which
is a fundamental building block in digital design.
The circuit will sum three bits and display the 2-bit output with LEDs.
- Write the truth table for each output.
- Write a logic equation for each output.
Lab work
-
Draw a circuit diagram using standard gate symbols.
-
Simulate the circuit in the Xilinx environment.
-
Make a wire list from your circuit diagram, listing exactly which pins
of which chips to connect together.
Don't forget to list the power connections!
-
Build the circuit using discrete (multiple chips) on the protokit.
-
Demonstrate the working circuit and simulation to the TA.
Report
The lab report for this lab is relatively simple.
You should make it look like the sample on the web, in that you should
follow the format, and describe what you did and the results of the
simulation.
You must include the truth table, logic equations, logic diagram, and
wire list in your write up.
Submit your lab report as a postscript (or HTML) file by e-mailing it as an
attachment to the TA of your lab section.
Also, submit the prelab for next week's lab assignment.
Lab 3 prelab
- Read and understand lab 3
- Devise a scheme to subtract by adding.
Describe the scheme in words and in logic equations.
- What is the logic equation for the Cout signal (you may express
it in terms of intermediate signal names, if you show how those
signals are computed)?
- Draw hierarchical block diagrams of your 4-bit circuit, showing how
the 4-bit sum is generated from single-bit blocks, and showing how a
single-bit block does the computation. You may use a full-adder cell
as a component in the block diagram.
CE home
CMPE 100 home page
Questions about page content should be directed to
Kevin Karplus
Computer Engineering
University of California, Santa Cruz
Santa Cruz, CA 95064
USA
karplus@cse.ucsc.edu
1-831-459-4250